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a/d type recorder 8-bit flash mcu HT83F22 revision: v.1.00 date: ??? i? 01? ? 011 ???i? 01? ? 011
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ? ???i? 01? ? 011 rev. 1.00 3 ???i? 01? ? 011 table of contents eates cpu featu?es .......................................................................................................................... 1 pe?i?he?a? featu?es .................................................................................................................. 1 gene?a? desc?i?tion .......................................................................................... ? b?ock diag?am ................................................................................................... 3 pin ?ssignment ................................................................................................. 3 pin desc?i?tion ................................................................................................. 4 ?bso?ute maximum ratings ............................................................................. 5 d.c. cha?acte?istics .......................................................................................... 6 dac and power amplifer electrical characteristics automatic gain control electrical characteristics comparator electrical characteristics power on reset (ac+dc) electrical characteristic c?ocking and pi?e?ining .......................................................................................................... 11 p?og?am counte? .................................................................................................................... 1? stack ...................................................................................................................................... 13 ??ithmetic and logic unit C ?lu ............................................................................................ 13 f?ash p?og?am memo?y .................................................................................. 14 st?uctu?e ................................................................................................................................. 14 s?ecia? vecto?s ...................................................................................................................... 14 look-u? tab?e ......................................................................................................................... 14 tab ?e p?og?am exam??e ......................................................................................................... 15 in ci?cuit p?og?amming .......................................................................................................... 15 data memo?y ................................................................................................... 18 st?uctu?e ................................................................................................................................. 18 s?ecia? function registe? desc?i?tion ......................................................... 19 indi?ect ?dd?essing registe?s C i?r0? i?r1 .......................................................................... 19 memo?y pointe?s C mp0? mp1 ............................................................................................... 19 bank pointe? C bp .................................................................................................................. ?0 ?ccumu?ato? C ?cc ................................................................................................................ ?1 p?og?am counte? low registe? C pcl ................................................................................... ?1 look-u? tab? e registe? s C tblp ? tbhp ? tblh ...................................................................... ?1 status registe? C st ? tus ..................................................................................................... ?1 time ? registe? s ...................................................................................................................... ?? osci??ato? ......................................................................................................... ?3 osci??ato? ove?view ................................................................................................................ ?3 system clock confgurations ................................................................................................. ?3
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ? ???i? 01? ? 011 rev. 1.00 3 ???i? 01? ? 011 exte?na? c?ysta?/ ce?amic osci??ato? C hxt ........................................................................... ?4 exte?na? rc osci??ato? C erc ................................................................................................ ?5 inte?na? rc osci??ato? C hirc ................................................................................................ ?5 exte?na? 3?.768khz c?ysta? osci??ato? C lxt ......................................................................... ?6 lxt osci ??ato? low powe? function ....................................................................................... ?7 inte?na? 3?khz osci??ato? C lirc ............................................................................................ ?7 su???ementa?y osci??ato?s ..................................................................................................... ?7 operating modes and system clocks .......................................................... 28 system c?ocks ....................................................................................................................... ?8 system o?e?ation modes ....................................................................................................... ?9 cont?o? registe? ..................................................................................................................... 30 fast wake C u ? ...................................................................................................................... 31 o?e? ating mode switching and wake-u? ............................................................................... 3? norm? l mode to slow mode switching ............................................................................ 3? slow mode to norm? l mode switching ............................................................................ 34 ente?ing the sleep0 mode ................................................................................................... 34 ente?ing the sleep1 mode ................................................................................................... 34 ente?ing the idle0 mode ....................................................................................................... 34 ente?ing the idle1 mode ....................................................................................................... 35 standby cu??ent conside?ations ............................................................................................ 35 wake-u ? ................................................................................................................................. 35 p?og?amming conside?ations ................................................................................................. 36 watchdog timer .............................................................................................. 37 watchdog time ? c?ock sou?ce ............................................................................................... 37 watchdog time ? cont?o? registe? .......................................................................................... 37 watchdog time ? o?e?ation .................................................................................................... 38 reset and initia?isation ........................................................................................................... 39 reset functions ..................................................................................................................... 39 reset initia? conditions .......................................................................................................... 4? input/output ports .......................................................................................... 44 pu??-high resisto?s ................................................................................................................. 45 po?t ? wake-u ? ...................................................................................................................... 45 i/o po?t cont?o? registe?s ...................................................................................................... 45 i/o pin st?uctu?es ................................................................................................................... 46 p?og?amming conside?ations ................................................................................................. 46 timer modules C tm ....................................................................................... 48 int?oduction ............................................................................................................................ 48 tm o?e?ation ......................................................................................................................... 48 tm c?ock sou?ce .................................................................................................................... 49 tm inte??u?ts .......................................................................................................................... 49 tm exte?na? pins .................................................................................................................... 49 tm in?ut/out?ut pin cont?o? registe?s .................................................................................. 50 p?og?amming conside?ations ................................................................................................. 5?
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 4 ???i? 01? ? 011 rev. 1.00 5 ???i? 01? ? 011 com? act ty?e tm .................................................................................................................. 53 com? act tm o?e?ation .......................................................................................................... 53 com? act ty? e tm registe? desc?i?tion ................................................................................. 54 com? act ty? e tm o?e? ating modes ..................................................................................... 57 com?a?e match out?ut mode ................................................................................................ 57 time ?/counte? mode .............................................................................................................. 59 pwm out?ut mode ................................................................................................................. 59 enhanced type tm C etm .............................................................................. 61 enhanced tm o ?e?ation ........................................................................................................ 61 enhanced ty ? e tm registe? desc?i?tion ............................................................................... 6? enhanced ty ? e tm o?e? ating modes .................................................................................... 67 com?a?e out?ut mode ........................................................................................................... 68 time ?/counte? mode .............................................................................................................. 70 pwm out?ut mode ................................................................................................................. 70 sing?e pu?se out?ut mode ..................................................................................................... 73 ca?tu?e in?ut mode ............................................................................................................... 75 timer/event counter C tmr ........................................................................... 76 confguring the timer/event counter input clock source ..................................................... 76 time ? registe? C tmr ............................................................................................................ 77 time ? cont?o? registe? C tmrc ............................................................................................. 77 time ? mode ............................................................................................................................ 79 event counte? mode .............................................................................................................. 79 pu?se width ca?tu?e mode .................................................................................................... 80 p?esca?e? ................................................................................................................................ 81 i/o inte?facing ......................................................................................................................... 81 p?og?amming conside?ations ................................................................................................. 81 time ?/event counte? p?og?am exam??e ................................................................................ 8? analog to digital converter ........................................................................... 83 ?/d ove?view ......................................................................................................................... 83 ?/d conve?te? registe? desc?i?tion ....................................................................................... 83 ?/d conve?te? data registe?s C ?drl? ?drh ...................................................................... 84 ?/d conve?te? cont?o? registe?s C ?dcr0? ?dcr1? ?cer .................................................. 84 ?/d o?e?ation ........................................................................................................................ 87 ?/d in?ut pins ........................................................................................................................ 88 summa?y of ?/d conve?sion ste?s ........................................................................................ 89 p?og?amming conside?ations ................................................................................................. 90 ?/d t ?ansfe? function ............................................................................................................ 90 ?/d p?og?amming exam??e .................................................................................................... 91 comparator ..................................................................................................... 93 com?a?ato? o?e?ation ........................................................................................................... 93 com?a?ato? registe?s ............................................................................................................ 93 com?a?ato? inte??u?t .............................................................................................................. 94 p?og?amming conside?ations ................................................................................................. 94
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 4 ???i? 01? ? 011 rev. 1.00 5 ???i? 01? ? 011 serial interface module C sim ........................................................................ 95 spin inte?face ........................................................................................................................ 95 simn registe?s list ................................................................................................................ 97 spi communication ............................................................................................................. 100 i ? c inte?face ......................................................................................................................... 101 i ? c inte?face o?e?ation ......................................................................................................... 10? i ? cn bus communication ..................................................................................................... 107 i ? cn bus sta?t signa? ............................................................................................................ 108 s?ave ?dd?ess ...................................................................................................................... 108 i ? cn bus read/w ?ite signa? ................................................................................................. 108 i ? cn bus s?ave ?dd?ess ?cknow?edge signa? ...................................................................... 108 i ? c bus data and ?cknow?edge signa? ................................................................................ 109 peripheral clock output ............................................................................... 111 pe?i?he?a? c?ock o?e?ation .................................................................................................. 111 interrupts ....................................................................................................... 112 inte??u?t registe?s ................................................................................................................ 11 ? inte??u?t o?e?ation ............................................................................................................... 117 exte?na? inte??u?t .................................................................................................................. 118 com?a?ato? inte??u?t ............................................................................................................ 119 mu?ti-function inte??u?t ......................................................................................................... 119 ?/d conve?te? inte??u?t ........................................................................................................ 119 time ?/event counte? inte??u?t .............................................................................................. 119 time base inte ??u?ts ............................................................................................................ 1?0 se?ia? inte?face modu?e inte??u?ts ........................................................................................ 1?1 exte?na? pe?i?he?a? inte??u?t ................................................................................................ 1?1 lvd inte ??u?t ........................................................................................................................ 1?? tm inte??u?ts ........................................................................................................................ 1?? inte??u? t wake-u? function .................................................................................................. 1?? p?og?amming conside?ations ............................................................................................... 1?3 power down mode and wake-up ................................................................. 124 ente?ing the idle o? sleep mode ...................................................................................... 1?4 standby cu??ent conside?ations .......................................................................................... 1?4 wake-u ? ............................................................................................................................... 1?4 low voltage detector C lvd ........................................................................ 125 lvd registe ? ........................................................................................................................ 1?5 lvd o ?e?ation ...................................................................................................................... 1?6 scom function fo? lcd ...................................................................................................... 1?6 lcd o?e?ation ..................................................................................................................... 1?6 lcd bias cont?o? ................................................................................................................. 1?7 digitia? to ?na?og conve?te? C d? c ...................................................................................... 1?8 audio power amplifer ................................................................................. 129 power amplifer .................................................................................................................... 1?9 microphone amplifer ................................................................................... 130
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 6 ???i? 01? ? 011 rev. 1.00 7 ???i? 01? ? 011 amplifer overview ............................................................................................................... 130 ?utomatic gain cont?o? registe? C ?gcc ........................................................................... 131 ?utomatic gain cont?o? C ?gc ............................................................................................ 13? two-stage amplifer .............................................................................................................. 133 switched ca?acito? fi?te? C scf .......................................................................................... 133 scf clock ...................................................................................................... 133 confguration options .................................................................................. 134 application circuits ...................................................................................... 136 instruction set ............................................................................................... 137 int?oduction .......................................................................................................................... 137 inst? uction timing ................................................................................................................. 137 moving and t ?ansfe??ing data .............................................................................................. 137 ??ithmetic o?e?ations ........................................................................................................... 137 logica? and rotate o?e?ations ............................................................................................. 137 b?anches and cont?o? t ?ansfe? ............................................................................................ 138 bit o?e?ations ...................................................................................................................... 138 tab ?e read o?e?ations ........................................................................................................ 138 othe? o?e?ations .................................................................................................................. 138 instruction set summary ............................................................................. 139 tab ?e conventions ................................................................................................................ 139 instruction defnition .................................................................................... 141 package information .................................................................................... 151 48-? in lqfp (7mmx7mm) out?ine dimensions ................................................................... 151
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 6 ???i? 01? ? 011 rev. 1.00 7 ???i? 01? ? 011 features cpu features operating voltage: f sys = 8mhz: 2.2v~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 20mhz: 4.5v~5.5v up to 0.2s instruction cycle with 20mhz system clock at v dd =5v power down and wake-up functions to reduce power consumption five oscillators: external crystal - hxt external 32.768khz crystal - lxt external rc - erc internal rc - hirc internal 32khz rc - lirc multi-mode operation: normal, slow, idle and sleep fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components all instructions executed in one or two instruction cycles table read instructions 63 powerful instructions up to 8-level subroutine nesting bit manipulation instruction peripheral features flash program memory: 4kx16 ram data memory: 384x8 watchdog timer function up to 24 bidirectional i/o lines software controlled 4-scom lines lcd driver with1/2 bias multiple pin-shared external interrupts multiple timer module for time measurement, input capture, compare match output, pwm output or single pulse output function single 8-bit programmable timer/event counter with overfow interrupt and prescaler two serial interface modules with dual spi and i 2 c interfaces single comparator dual time-base functions for generation of fxed time interrupt signals up to 8 channel 12-bit resolution a/d converter single channel 12-bit d/a converter output signal power amplifer input signal amplifer with automatic gain control - agc switch capacitor filter function low voltage reset function low voltage detect function package types: 48lqfp
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 8 ???i? 01? ? 011 rev. 1.00 9 ???i? 01? ? 011 general description the HT83F22 is an a/d type 8-bit high performance flash memory mcu which includes a digital voice recorder, synthesizer and tone generator. it is specifically designed for applications which require multiple i/os and sound effects, such as voice and melodies. additionally, it can provide various sampling rates and beats, tone levels, tempos for speech synthesisers and melody generators. furthermore, with the internal amplifer, auto gain control, scf filter and the fast 12-bit a/d converter features, this device provides a means of implementing digital audio recorder applications. offering users the convenience of flash memory multi-programming features, this device also includes a wide range of functions and features. analog features include a multi-channel 12-bit a/d converter and comparator. multiple and extremely flexible timer modules provide timing, pulse generation and pwm generation functions. communication with the outside world is catered for by including fully integrated spi or i 2 c interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments.it also includes an integrated high quality, voltage type dac output, a two-stage amplifer with auto gain control for microphone input signal amplifcation and a power amplifier for speaker driving. the external interrupt can be triggered with falling edges or both falling and rising edges. a full choice of hxt, lxt, erc, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure that the devices will find excellent use in applications such as voice recorder, answering machine, electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. this device is fully supported by the holtek range of fully fun ctional development and programming tools, providing a means for fast and effcient product development cycles.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 8 ???i? 01? ? 011 rev. 1.00 9 ???i? 01? ? 011 block diagram
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HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 10 ???i? 01? ? 011 rev. 1.00 11 ???i? 01? ? 011 pin description the pins on this device can be referenced by their port name, e.g. pa.0, pa.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, serial port pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pin name function op i/t o/t pin-shared mapping p ?0~p ?7 po?t ? p? wu p ?pu st cmos pb0~pb7 po?t b pbpu st cmos pc0~pc7 po?t c pcpu st cmos ?n0~?n7 ?dc in?ut ?cer ?n p ?0~p ?7 vref ?dc ?efe?ence in?ut ?dcr1 ?n pb5 c- com?a?ato? in?ut cpc ?n p? 3 c+ com?a?ato? in?ut ?n p ?? cx com?a?ato? out?ut cmos p? 0 tck0? tck1? tmr tc0? tc1? tmr in?ut st p ??? p ?4? pc? tp0_0? tp0_1 tm0 i/o tmpc0 st cmos p ?0? pc5 tp1? tm1 i/o tmpc0 st cmos p? 1 tp1b_0? tp1b_1? tp1b_? tm1 i/o tmpc0 st cmos pc0? pc1?pc5 int0? int1 ext. inte??u?t 0? 1 st p ?3? p ?4 pint pe?i?he?a? inte??u?t st pc3 pck pe?i?he?a? c?ock out?ut cmos pc? sdi1 spi1 data in?ut st p? 6 sdo1 spi1 data out?ut ? cmos p? 5 scs1 spi1 s?ave se?ect st cmos pc1 sck1 spi1 se?ia? c?ock st cmos p ?7 scl1 i ? c1 c?ock st nmos p? 7 sd?1 i ? c1 data st nmos p? 6 sdi0 spi0 data in?ut st sdo0 spi0 data out?ut cmos scs0 spi0 s?ave se?ect st cmos sck0 spi0 se?ia? c?ock st cmos scl0 i ? c0 c?ock st nmos sd?0 i ? c0 data st nmos scom0~scom3 scom0~scom3 scomc scom pc0?pc1? pc6?pc7 osc1 hxt/erc ?in co hxt pb1 osc? hxt ?in co hxt pb? xt1 lxt ?in co lxt pb3 xt? lxt ?in co lxt pb4 res reset in?ut co st pb0 ?ud d?c out?ut ?n sp+? sp- 3rzhudpsolhurxwsxw ?n ?ud_in 3rzhudpsolhulqsxw ?n vbi?s *&dqg3rzhudpsolhu vo?tage bias ?efe?ence pwr
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 10 ???i? 01? ? 011 rev. 1.00 11 ???i? 01? ? 011 pin name function op i/t o/t pin-shared mapping min mic?o?hone in?ut ?n mout mic?o?hone out?ut ?n ?in amplifer input ?n ?out amplifer output ?n p? 0 ?gc ?gc in?ut ?n vss g?ound pwr vdd io? co?e powe? pwr vcc?? ?dc powe? pwr vcc?5 sim0 spi powe? pwr vcc?6 ?gc powe? pwr vcc?7 powe? ?m? powe? pwr vcc?8 d?c powe? pwr nc no connection vss?? ?dc g?ound pwr vss?6 ?gc g?ound pwr vss?7 powe? ?m? g?ound pwr vss?8 d?c g?ound pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is the device power supply while avdd is the adc power supply. the avdd pin is bonded together internally with vdd. **: vss is the device ground pin while avss is the adc ground pin. the avss pin is bonded together internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. absolute maximum ratings supply voltage ................................................................................................ v ss -0.3v to v ss +6.0v input voltage .................................................................................................. v ss -0.3v to v dd +0.3v i ol total ..................................................................................................................................... 80ma total power dissipation ........................................................................................................ 500mw storage temperature .................................................................................................. -50 c to 125c operating temperature ................................................................................................ -40 c to 85 c i oh tatal .................................................................................................................................... -80ma note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcat ion is not implied and prolonged exposure to extreme conditions may affect device reliability.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1? ???i? 01? ? 011 rev. 1.00 13 ???i? 01? ? 011 d.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 o?e? ating vo?tage (hxt) f sys =8mhz ?.? 5.5 v f sys =10mhz ?.7 5.5 v f sys =1?mhz 3.3 5.5 v f sys =16mhz 4.5 5.5 v v dd? o?e? ating vo?tage (erc) f sys =6mhz ?.? 5.5 v f sys =8mhz ?.7 5.5 v f sys =1?mhz 4.5 5.5 v v dd3 o?e? ating vo?tage (hirc) f sys =8mhz ?.? 5.5 v f sys =1?mhz ?.7 5.5 v i dd1 o?e?ating cu??ent (hxt ? f sys =f h ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? f h =8mhz? ? dc off? wdt enab ?e 0.8 1.5 m? 5v ?.5 4 m? 3v no ?oad? f h =10mhz? ? dc off? wdt enab ?e 1.3 ?.0 m? 5v 3.3 5.0 m? 3v no ?oad? f h =1?mhz? ? dc off? wdt enab ?e 1.6 ?.4 m? 5v 4.0 6.0 m? 3v no ?oad? f h =16mhz? ? dc off? wdt enab ?e ?.0 3.0 m? 5v 5.1 7.7 m? 5v no ?oad? f h =?0mhz? ? dc off? wdt enab ?e 6.? 9.3 m? i dd? o?e?ating cu??ent (erc? f sys =f h ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? f h =6mhz? ? dc off? wdt enab ?e 0.9 1.4 m? 5v ?.0 3.0 m? 3v no ?oad? f h =8mhz? ? dc off? wdt enab ?e 1.3 ?.0 m? 5v ?.8 4.5 m? 3v no ?oad? f h =1?mhz? ? dc off? wdt enab ?e 1.9 ?.9 m? 5v 4.0 6.0 m? 5v no ?oad? f h =16mhz? ? dc off? wdt enab ?e 5.0 7.5 m? i dd3 o?e?ating cu??ent (hirc? f sys =f h ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? f h =4mhz? ? dc off? wdt enab ?e 0.7 1.1 m? 5v 1.5 ?.5 m? 3v no ?oad? f h =8mhz? ? dc off? wdt enab ?e 1.3 ?.0 m? 5v ?.8 4.5 m? 3v no ?oad? f h =1?mhz? ? dc off? wdt enab ?e ?.1 3.? m? 5v 4.0 6.0 m? i dd4 o?e?ating cu??ent (lxt ? f sys =f l ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? f h =1?mhz? f l =f h /?? ? dc off? wdt enab?e 0.9 1.4 m? 5v ?.1 3.3 m? 3v no ?oad? f h =1?mhz? f l =f h /4? ? dc off? wdt enab?e 0.6 0.9 m? 5v 1.7 ?.6 m? 3v no ?oad? f h =1?mhz? f l =f h /8? ? dc off? wdt enab?e 0.4 0.6 m? 5v 1.4 ?.1 m? 3v no ?oad? f h =1?mhz? f l =f h /16? ? dc off? wdt enab?e 0.4 0.6 m? 5v 1.? 1.8 m? 3v no ?oad? f h =1?mhz? f l =f h /3?? ? dc off? wdt enab?e 0.3 0.5 m? 5v 1.1 1.7 m? 3v no ?oad? f h =1?mhz? f l =f h /64? ? dc off? wdt enab?e 0.3 0.5 m? 5v 1.1 1.7 m? i dd5 o?e?ating cu??ent (lxt ? f sys =f l =f lxt ? f s =f sub =f lxt ) 3v no ?oad? ? dc off? wdt enab?e? lxtlp=0 70 110 u? 5v ?10 3?0 u? 3v no ?oad? ? dc off? wdt enab?e? lxtlp =1 70 110 u? 5v ?10 3?0 u? i dd6 o?e?ating cu??ent (lirc osc? f sys =f l =f lirc ? f s =f sub =f lirc ) 3v no ?oad? ? dc off? wdt enab?e 68 100 u? 5v ?10 3?0 u?
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1? ???i? 01? ? 011 rev. 1.00 13 ???i? 01? ? 011 symbol parameter test conditions min. typ. max. unit v dd conditions i dd7 o?e?ating cu??ent (lxt+lirc? f sys =f l =f lxt ? f s =f sub =f lirc ) 3v no ?oad? ? dc off? wdt enab?e? lxtlp =0 68 100 u? 5v ?10 3?0 u? i stb1 stanby cu??ent (id?e) (hxt ? f sys =f h ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =1?mhz 0.5 1.0 m? 5v 1.? ?.0 m? i stb? stanby cu??ent (id?e) (hxt ? f sys =off ? f s =t1) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =1?mhz 1.3 3.0 a 5v ?.? 5.0 a i stb3 stanby cu??ent (id?e) (hxt ? f sys =off ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =1?mhz 1.3 3.0 a 5v ?.? 5.0 a i stb4 stanby cu??ent (id?e) (erc? f sys =off ? f s =f sub =f lxt ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =1?mhz 1.3 3.0 a 5v 1.8 5.0 a i stb5 stanby cu??ent (id?e) (hirc? f sys =off ? f s =f sub =f lirc ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =1?mhz 0.9 3.0 a 5v 1.6 5.0 a i stb6 stanby cu??ent (id?e) (hxt ? f sys =f l ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? system h? lt ? ? dc off? wdt enab?e? f sys =1?mhz/64 0.5 0.8 m? 5v 1.? 1.8 m? i stb7 stanby cu??ent (id?e) (hxt ? f sys =off ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? system h? lt ? ? dc off? wdt enab?e? f sys =1?mhz/64 1.3 3.0 a 5v ?.? 5.0 a i stb8 stanby cu??ent (id?e) (lxt ? f sys =f l =f lxt ? f s =f sub =f lxt ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =3?768hz 1.9 4.0 a 5v 3.3 7.0 a i stb9 stanby cu??ent (id?e) (lxt ? f sys =off ? f s =t1) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =3?768hz 1.3 3.0 a 5v ?.1 5.0 a i stb10 stanby cu??ent (id?e) (lxt ? f sys =off ? f s =f sub =f lxt ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =3?768hz 1.3 3.0 a 5v ?.1 5.0 a i stb11 stanby cu??ent (id?e) (lirc? f sys =off ? f s =f sub =f lirc ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =3?khz 1.3 3.0 a 5v ?.? 5.0 a i stb1? stanby cu??ent (id?e) (lxt ? f sys =off ? f s =f sub =f lirc ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =3?768hz 1.3 3.0 a 5v ?.? 5.0 a i stb13 stanby cu??ent (s?ee?) (hxt ? f sys =off ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? system h? lt ? ?dc off ? wdt disab?e? f sys =1?mhz 0.1 1 a 5v 0.3 ? a i stb14 stanby cu??ent (s?ee?) (hxt ? f sys =off ? f s =f sub =f ltx ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =1?mhz 1.3 5 a 5v ?.1 10 a i stb15 stanby cu??ent (s?ee?) (hxt ? f sys =off ? f s =f sub =f lirc ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =1?mhz 1.3 5 a 5v ?.? 10 a i stb16 stanby cu??ent (s?ee?) (lxt ? f sys =off ? f s =f sub =f lxt o? f lirc ) 3v no ?oad? system h? lt ? ? dc off? wdt disab?e? f sys =3?768hz 0.1 1.0 a 5v 0.3 ?.0 a
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 14 ???i? 01? ? 011 rev. 1.00 15 ???i? 01? ? 011 symbol parameter test conditions min. typ. max. unit v dd conditions i stb17 stanby cu??ent (s?ee?) (lxt ? f sys =off ? f s =f sub =f lxt ) 3v no ?oad? system h? lt ? ?dc off ? wdt enab?e? f sys =3?768hz 1.3 3.0 a 5v ?.? 5.0 i stb18 stanby cu??ent (s?ee?) (hxt ? f sys =off ? f s =f sub =f lxt o? f lirc ) 5v no ?oad? system h? lt ? ?dc off ? wdt disab?e? f sys =1?mhz? lvr enab ? e and lvden=1 60 90 a v il1 in? ut low vo?tage fo? i/o po?ts o? in?ut ?ins exce?t res ?in 0 0.3v dd v v ih1 in? ut high vo?tage fo? i/o po?ts o? in?ut ?ins exce?t res ?in 0.7v dd v dd v v il? in? ut low vo?tage ( res ) 0 0.4v dd v v ih? in? ut high vo?tage ( res ) 0.9v dd v dd v v lvr1 low vo ? tage reset vo? tage lvr enab ?e? ?.1v o?tion -5% ty ?. ?.1 +5% ty ?. v v lvr ? lvr enab ?e? ?.55v o?tion ?.55 v v lvr3 lvr enab ?e? 3.15v o?tion 3.15 v v lvr4 lvr enab ?e? 4.?v o?tion 4.? v i lvr low vo ? tage reset cu??ent 3v lvr enab ?e? lvden=0 48 70 a 5v 55 80 u? v lvd1 low vo ?tage detecto? vo ?tage lvden = 1 ? v lvd = ?.0v -5% ty ?. ?.0 +5% ty ?. v v lvd ? lvden = 1 ? v lvd = ?.?v ?.? v v lvd3 lvden = 1 ? v lvd = ?.4v ?.4 v v lvd4 lvden = 1 ? v lvd = ?.7v ?.7 v v lvd5 lvden = 1 ? v lvd = 3.0v 3.0 v v lvd6 lvden = 1 ? v lvd = 3.3v 3.3 v v lvd7 lvden = 1 ? v lvd = 3.6v 3.6 v v lvd8 lvden = 1 ? v lvd = 4.4v 4.4 v i lvd1 low vo ?tage detecto? cu??ent 3v lvr disab ?e? lvden = 1 47 70 a i lvd ? lvr enab ?e? lvden = 1 49 75 a i lvd1 low vo ?tage detecto? cu??ent 5v lvr disab ?e? lvden = 1 5? 75 a i lvd ? lvr enab ?e? lvden = 1 55 80 a i ol i/o po?t sink cu??ent 3v v ol =0.1v dd 4 8 m? 5v v ol =0.1v dd 10 ?0 m? i oh i/o po?t? sou?ce cu??ent 3v v oh =0.9v dd -? -4 m? 5v v oh =0.9v dd -5 -10 m? v scom v dd /? vo?tage fo? lcd com ?o?t (inven=0) no ?oad 0.475 0.5 0.5?5 v dd r ph pu ?? -high resistance of i/o po?ts 3v ?0 60 100 k 5v 10 30 50 k ?v dd ?na?og o?e?ating vo?tage v ref = ?v dd ?.7 5.5 v v ?d ?d in? ut vo?tage 0 ?v dd / v ref v v ref ?dc in?ut ?efe?ence vo?tage ?ange ?v dd =3v 1.6 ?v dd + 0.1 v ?v dd =5v 1.6 ?v dd + 0.1 v v bg bandga? ?efe?ence with buffe ? vo?tage -3% ty ?. 1.?5 +3% ty ?. v i bg bandga? ?efe?ence with buffe ? d?iving cu??ent v bg is used? lvr disab?e? lvden=0 ?00 ?60 a dnl diffe ?entia? non-?inea?ity 3v v ref = ?v dd =v dd ? t ?d =0.5 s -3 +3 lsb 5v v ref = ?v dd =v dd ? t ?d =0.5 s -3 +3 lsb
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 14 ???i? 01? ? 011 rev. 1.00 15 ???i? 01? ? 011 symbol parameter test conditions min. typ. max. unit v dd conditions inl integ?a? non-?inea?ity 3v v ref = ?v dd =v dd ? t ?d =0.5 s -4 +4 lsb 5v v ref = ?v dd =v dd ? t ?d =0.5 s -4 +4 lsb i ?dc on?y ?dc enab?e? othe?s disab?e 3v no ?oad (t ?d =0.5s ) 1.0 ?.0 m? 5v no ?oad (t ?d =0.5s ) 1.5 3.0 m? po inte?na? ? mp out?ut powe? 3v (thd+n)/s<=1%? rl=8_ vin=1khz sinewave 90 mw (thd+n)/s<=10%? rl=8_ vin=1khz sinewave 1?5 mw 5v (thd+n)/s<=1%? rl=8_ vin=1khz sinewave 385 mw (thd+n)/s<=10%? rl=8_ vin=1khz sinewave 490 mw io ?ud cu??ent sou?ce 3v v oh =0.9v dd -3 m? 5v v oh =0.9v dd -10 m? dac and power amplifer electrical characteristics ta= ?5c dac symbol parameter test conditions min. typ. max. unit v dd conditions thd+n thd+n note1 5v 10k load -55 db power amplifer g gain 5v note? 10 v/v thd+n thd+n note1 5v 8 load -51 db 5v 16 load -54 db pout out?ut powe? 5v 8 load, thd=1% 710 mw 5v 16 load, thd=1% 540 mw 1rwhvlqhzdyhlqsxw#n+]g% 1rwhvlqhzdyhlqsxw#n+]p9ss automatic gain control electrical characteristics parameter symbol condition specification unit min. typ. max. p?eam? in?ut im?edance rmic v dd =5v ?0 k mic in? ut swing vo?tage vmic v dd =5v ? t ?=?5c 1 ?00 mv?-? p?eam? gain ?pre v dd =5v ? t ?=?5c ?? db gain of p?og?ammab?e gain amplifer ?pg? v dd =5v ? t ?=?5c rgs=000 rgs=001 rgs=010 rgs=011 rgs=100 rgs=101 rgs=110 rgs=111 1.16 1.56 ?.?? ?.91 5.09 8.91 13.8? ?5.97 v/v
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 16 ???i? 01? ? 011 rev. 1.00 17 ???i? 01? ? 011 a.c. characteristics symbol parameter v dd condition min. typ. max. unit f sys1 system c?ock (hxt) ?.?~5.5v ? 8 mhz ?.7~5.5v ? 10 mhz 3.3~5.5v ? 1? mhz 4.5~5.5v ? 16 mhz f sys? system c?ock (erc) 5v ta = ?5 c exte?na? r erc = 1?0 k -? %ty?. 8 +? %ty?. mhz f sys3 system c?ock (hirc) 5v ta = ?5 c -? %ty?. 8 +? %ty?. mhz f sys4 system c?ock (lxt) 3?768 hz f timer time ? i/p f?equency (tmr) ?.?~5.5v ? 8 mhz ?.7~5.5v ? 10 mhz 3.3~5.5v ? 1? mhz 4.5~5.5v ? 16 mhz f lirc system c?ock (3?k rc) 5v ta = ?5 c -10%ty ?. 3? +10%ty ?. khz t res exte?na? ?eset ?ow ?u?se width 1 s t sst system sta?t-u? time? ?e?iod (wake-u? f?om h? lt) f sys =hxt o ? lxt 10?4 t sys f sys =erc o? hirc 15~16 f sys =lirc 1~? t int inte??u?t ?u?se width 1 s t lvr low vo ?tage width to reset 1?0 ?40 480 s t lvd low vo ?tage width to inte??u?t ?0 60 1?0 s t lvds lvdo stab ?e time fo? a?? v lvd ? lvr disab ?e 15 s t bgs vbg tu?n on stab?e time 10 ms t ?d ?/d c?ock pe?iod ?.7~5.5v 0.5 100 s t ?dc ? d conve? sion time (note?) ?.7~5.5v 1? bit ?dc 16 t ?d t on?st ?dc on to ?dc sta?t ?.7~5.5v ? s note: 1. t 1/f , as the resistor tolerance will infuence the frequency a precision resistor is recommended. 3. to maintain the accuracy of the internal hirc oscillator frequency, a 0.1f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. comparator electrical characteristics symbol parameter v dd condition min. typ. max. unit com?a?ato? o?e?ating vo?tage ?.? 5.5 v com?a?ato? o?e?ating cu??ent 5v ?00 a com?a?ato? ?owe? down cu??ent 5v com?a?ato? disab?e 0.1 a v cmpos com?a?ato? in? ut offset vo?tage 5v -10 +10 mv v hys hyste?esis width 5v ?0 40 60 mv v cm com?a?ato? common mode vo?tage ?ange v ss v dd - 1.4v v ? ol com?a?ato? o?en ?oo? gain 60 80 db t pd com?a?ato? ?es?onse time 3v with 100mv ove?d?ive (note) ?00 400 ns 5v note: measured with comparator one input pin at v = (v -1.4)/2 while the other pin input transition from v to (v +100mv) or from v to (v -100mv).
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 16 ???i? 01? ? 011 rev. 1.00 17 ???i? 01? ? 011 power on reset (ac+dc) electrical characteristic symbol parameter v dd condition min. typ. max. unit v por v dd sta? t vo?tage to ensu?e powe?-on reset 100 mv r por ?c v dd rise rate to ensu?e powe?-on reset 0.035 v/ms t por minimum time fo ? v dd stays at v por to ensu?e powe?-on reset 1 ms system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc, lirc or erc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instr uctions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 18 ???i? 01? ? 011 rev. 1.00 19 ???i? 01? ? 011
? ? ? ? ? ? ? ? system clocking and pipelining
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is ex - ecuted except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruc - tion, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by load - ing the required address into the program counter. for conditional skip instructions, once the condi - tion has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc11~pc8 pcl7~pcl0 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 18 ???i? 01? ? 011 rev. 1.00 19 ???i? 01? ? 011 stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?0 ???i? 01? ? 011 rev. 1.00 ?1 ???i? 01? ? 011 flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, this flash device offers users the fexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 4kx16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.
porgram memory structure look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrd[m] or tabrdl[m] instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?0 ???i? 01? ? 011 rev. 1.00 ?1 ???i? 01? ? 011

table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is f00h which refers to the start address of the last page within the 4k program memory of the HT83F22. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re- insertion of the device. mcu programming pins function p? 0 se?ia? data in?ut/out?ut p ?? se?ia? c?ock res device reset vdd powe? su???y vss g?ound
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?? ???i? 01? ? 011 rev. 1.00 ?3 ???i? 01? ? 011 the program memory can be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. during the programming process the res pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the pa0 and pa2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address mov tblp,a ; is referenced mov a,0fh ; initialise high table pointer tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address f06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address f05h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?? ???i? 01? ? 011 rev. 1.00 ?3 ???i? 01? ? 011
note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. programmer pin mcu pins res pb0 d ?t? p? 0 clk p ?? programmer and mcu pins
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?4 ???i? 01? ? 011 rev. 1.00 ?5 ???i? 01? ? 011 data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. capacity banks 384x8 0: 80h~ffh 1: 80h~ffh ?: 80h~ffh bank 0, 1, 2 ram mapping ram mapping 00h i?r0 ?8h vol 01h mp0 ?9h 0?h i?r1 ??h sim0c0 03h mp1 ?bh sim0c1 04h bp ?ch sim0d 05h ?cc ?dh sim0?/sim0c? 06h pcl ?eh ?drl 07h tblp ?fh ?drh 08h tblh 30h ?dcr0 09h tbhp 31h ?dcr1 0?h st ? tus 3?h ?cer 0bh smod 33h ?gcc 0ch lvdc 34h cpc 0dh integ 35h 0eh wdtc 36h sim1c0 0fh tbc 37h sim1c1 10h intc0 38h sim1d 11h intc1 39h sim1?/sim1c? 1?h intc? 3?h tm0c0 13h intc3 3bh tm0c1 14h mfi0 3ch tm0dl 15h mfi1 3dh tm0dh 16h mfi? 3eh tm0?l 17h 3fh tm0?h 18h p? wu 40h tmpc0 19h p ?pu 41h 1?h p? 4?h
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?4 ???i? 01? ? 011 rev. 1.00 ?5 ???i? 01? ? 011 bank 0, 1, 2 ram mapping ram mapping 1bh p? c 43h 1ch pbpu 44h 1dh pb 45h tm1c0 1eh pbc 46h tm1c1 1fh pcpu 47h tm1c? ?0h pc 48h tm1dl ?1h pcc 49h tm1dh ??h tmrc 4?h tm1?l ?3h tmr 4bh tm1?h ?4h 4ch tm1bl ?5h misc 4dh tm1bh ?6h d?l 4eh scomc ?7h d?h 4fh bank0: 80h~ffh use? data ?am: 1?8*8 bit data memory special function register description most of the special function register details will be described in the relevant functional section; however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory p ointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?6 ???i? 01? ? 011 rev. 1.00 ?7 ???i? 01? ? 011 indirect addressing program example data .section data ? adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ? code ? org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: 7khlsudslhkhuhlvkdlkhhdsohvkd eyhuhihuhfhlvdhvshflf 50duhvvhv bank pointer C bp 7khdwd0hprulvglylghglqwrvhyhudodqnv6hohfwlqjwkhuhtluhgdwd0hpruduhdlv dfklhyhgvlqjwkhdqn3rlqwhu7khlwvariwkhdqn3rlqwhuduhvhgwrvhohfwdwd0hpru dqnva 7khdwd0hprulvlqlwldolvhgwrdqndiwhuduhvhwhfhswirud7wlphrwuhvhwlqwkh3rhu rq0rghlqklfkfdvhwkhdwd0hprudqnuhpdlqvqdiihfwhg,wvkroghqrwhgwkdwwkh 6shfldo)qfwlrqdwd0hprulvqrwdiihfwhgwkhdqnvhohfwlrqklfkphdqvwkdwwkh6shfldo )qfwlrq5hjlvwhuvfdqhdffhvvhgiurplwklqdqdqnluhfwodgguhvvlqjwkhdwd0hpru loododvuhvowlqdqnhlqjdffhvvhgluuhvshfwlyhriwkhydohriwkhdqn3rlqwhuffhvvlqj gdwdiurpdqnvrwkhuwkdqdqnpvwhlpsohphqwhgvlqj,qgluhfwdgguhvvlqj vrwkwkh3urjudp0hprudqgdwd0hpruvkduhwkhvdphdqn3rlqwhu5hjlvwhufduhpvwh wdnhqgulqjsurjudpplqj bit 7 6 5 4 3 2 1 0 dmbp1 dmbp0 bp registers list bp register bit 7 6 5 4 3 2 1 0 name dmbp1 dmbp0 r/w r/w r/w por 0 0 %lwa 8qlpsohphqwhguhdgdv bit 1 ~ 0 dmbp1, dmbp0 6hohfwdwd0hprudnv dn dn dn ghhg
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?6 ???i? 01? ? 011 rev. 1.00 ?7 ???i? 01? ? 011 accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller . with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf fag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?8 ???i? 01? ? 011 rev. 1.00 ?9 ???i? 01? ? 011 pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ?c c r/w r r r/w r/w r/w r/w por 0 0 x x x x x unknown bit 7, 6 unimplemented, read as 0 to : watchdog time-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation. c is also affected by a rotate through carry instruction. timer register s this device contains one 8-bit timer whose associated registers are known as tmr which is the location where the associated timers 8-bit value is located. its associated control register, known astmrc, contains the setup information for this timer. this 8-bit timer can be used to provide the clock source for the switch capacitor filter. note that all timer registers can be directly written to in order to preload their contents with fxed data to allow different time intervals to be setup.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 ?8 ???i? 01? ? 011 rev. 1.00 ?9 ???i? 01? ? 011 oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving . oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. type name freq. pins exte?na? c?ysta? hxt 400khz~?0mhz osc1/osc? exte?na? rc erc 8mhz osc1 inte?na? high s?eed rc hirc 4? 8 o? 1?mhz exte?na? low s?eed c?ysta? lxt 3?.768khz xt1/xt? inte?na? low s?eed rc lirc 3?khz oscillator types system clock confgurations there are fve methods of generating the system clock, three high speed oscillators and two low speed oscillators. the high speed oscillators are the external crystal/ceramic oscillator, external rc network oscillator and the internal 4mhz, 8mhz or 12mhz rc oscillator. the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768khz crystal oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 30 ???i? 01? ? 011 rev. 1.00 31 ???i? 01? ? 011

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? ?? system clock confgurations the actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator . external crystal/ ceramic oscillator C hxt the external crystal/ ceramic system oscillator is one of the high frequency oscillator choices, which is selected via configuration option. for most crystal oscillator configurations, the simple connection of a crystal across osc1 and osc2 will create the ne cessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specifcation.
? ? ?? crystal/resonator oscillator hxt
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 30 ???i? 01? ? 011 rev. 1.00 31 ???i? 01? ? 011 crystal oscillator c1 and c2 values crystal frequency c1 c2 1?mhz 0?f 0?f 8mhz 0?f 0?f 4mhz 0?f 0?f 1mhz 100?f 100?f note: c1 and c? va?ues a?e fo? guidance on? y. crystal recommended capacitor values external rc oscillator C erc using the erc oscillator only requires that a resistor, with a value between 56k and 2.4m , is connected between osc1 and vdd, and a capacitor is connected between osc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation frequency; the external capacitor has no infuence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an external 120k resistor connected and with a 5v voltage power supply and temperature of 25 c degrees, the oscillator will have a frequency of 8mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pb1, leaving pin pb2 free for use as a normal i/o pin. external rc oscillator erc internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fxed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25 c degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pb1 and pb2 are free for use as normal i/o pins.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 3? ???i? 01? ? 011 rev. 1.00 33 ???i? 01? ? 011 external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specification. the external parallel feedback resistor, rp, is required. some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins.
? ? ? ? ? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values c?ysta? f?equency c1 c? 3?.768khz 10?f 10?f note:1. c1 and c? va?ues a?e fo? guidance on? y. ?. r p =5m~10m is ?ecommended. 32.768khz crystal recommended capacitor values
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 3? ???i? 01? ? 011 rev. 1.00 33 ???i? 01? ? 011 lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the misc register. lxtlp bit lxt mode 0 quick sta?t 1 low-?owe? after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low- power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary oscillators the low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. these are the watchdog timer and the time base interrupts.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 34 ???i? 01? ? 011 rev. 1.00 35 ???i? 01? ? 011 operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either an hxt, erc or hirc oscillator, selected via a configuration option. the low speed system clock source can be sourced from internal clock f l. if f l is selected then it can be sourced by either the lxt or lirc oscillators, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the time base clock, f tbc . each of these internal clocks are sourced by either the lxt or lirc oscillators, selected via confguration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. f tbc f sys/ 4 tbck f sub f sys/ 4 f tb f s configu ? ation o ? tion time base wdt hxt erc hirc lirc lxt 6 - stage p ? esca ? e? high s ? eed osci ?? ation low s ? eed osci ?? ation low s ? eed osci ?? ation configu ? ation o ? tion high s ? eed osci ?? ation configu ? ation o ? tion f h f h /? f h /4 f h /8 f h /16 f h /3 ? f h /64 f l hlclk ? cks ? ~cks0 bits fast wake - u? f ? om sleep mode o ? idle mode cont ? o? (fo ? hxt on ? y) f sys f sub system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. together with f sys /4 it is also used as one of the clock sources for the watchdog timer. the f tbc clock is used as a source for the time base interrupt functions and for the tms.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 34 ???i? 01? ? 011 rev. 1.00 35 ???i? 01? ? 011 system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f sub f s f tbc norm? l mode on f h ~ f h /64 on on on slow mode on f l on on on idle0 mode off off on on/off on idle1 mode off on on on on sleep0 mode off off off off off sleep1 mode off off on on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt, erc or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~lcks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to "0". if the lvden is set to "1", it won't enter the sleep0 mode. sleep1 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the lvden is "1" or the watchdog timer function is enabled and if its clock source is chosen via confguration option to come from the f sub . idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer, tms and sim. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the watchdog timer clock, f s , will either be on or off depending upon the f s clock source. if the source is f sys /4 then the f s clock will be off, and if the source comes from f sub then f s will be on. idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer, tms, and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the watchdog timer clock, f s , will be on. if the source is f sys /4 then the f s clock will be on, and if the source comes from f sub then f s will be on.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 36 ???i? 01? ? 011 rev. 1.00 37 ???i? 01? ? 011 control register a single register, smod, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cs2~cs0 : the system clock selection when hlclk is "0" 000: f l (f lxt or f lirc ) 001: f l (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fse : fast wake-up control (only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f sub clock source is initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temporary system clock to provide a faster wake up time as the f sub clock is available. bit 3 o : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 ho : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indica tes when the high speed system oscillator is stable. this fag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the erc or hirc oscillator is used. bit 1 ide : idle mode control 0: disable 1: enable
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 36 ???i? 01? ? 011 rev. 1.00 37 ???i? 01? ? 011 this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast wake-up function has no effect because the f sub clock is stopped. the fast wake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscillator is selected as the normal mode system clock, and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator. if the erc or hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycles of the erc or hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these cases. fsten (sleep0 mode) (sleep1 mode) (idle0 mode) (idle1 mode) hxt 0 10? 4 hxt cyc?es 10? 4 hxt cyc?es 1~? hxt cyc?es 1 10? 4 hxt cyc?es 1~? f sub cyc?es (system ?uns with f sub frst for 1024 hxt cyc ?es and then switches ove? to ? un with the hxt c?ock) 1~? hxt cyc?es erc x 15~16 erc cyc?es 15~16 erc cyc?es 1~? erc cyc?es hirc x 15~16 hirc cyc?es 15~16 hirc cyc?es 1~? hirc cyc?es lirc x 1~? lirc cyc?es 1~? lirc cyc?es 1~? lirc cyc?es lxt x 10? 4 ltx cyc?es 10? 4 lxt cyc?es 1~? lxt cyc?es wake-u? times note that if the watchdog timer is disabled, which means that the lxt and lirc are all both off, then there will be no fast wake-up function available when the device wakes-up from the sleep0 mode.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 38 ???i? 01? ? 011 rev. 1.00 39 ???i? 01? ? 011

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? operating mode switching and wake-up the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/ slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or fl. if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when the device moves between the various operating modes. normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 38 ???i? 01? ? 011 rev. 1.00 39 ???i? 01? ? 011
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HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 40 ???i? 01? ? 011 rev. 1.00 41 ???i? 01? ? 011 slow mode to normal mode switching in slow mode the system uses eit her the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "011", "100", "101", "110" or "111". as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: the system clock, wdt clock and time base clock will be stopped and the application program will stop at the "halt" instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: the system clock and time base clock will be stopped and the application program will stop at the "halt" instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. the i/o ports will maintain their present conditions. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "halt" nstruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in wdtc register equal to "0". when this instruction is executed under the conditions described above, the following will occur: the system clock will be stopped and the application program will stop at the "halt" instruction, but the time base clock and f sub clock will be on. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 40 ???i? 01? ? 011 rev. 1.00 41 ???i? 01? ? 011 the i/o ports will maintain their present conditions. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle1 mode there is only one way for the device to en ter the idle1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in wdtc register equal to "1". when this instruction is executed under the with conditions described above, the following will occur: the system clock and time base clock and f sub clock will be on and the application program will stop at the "halt" instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt is enabled regardless of the wdt clock source which originates from the f sub clock or from the system clock. the i/o ports will maintai n their present conditions. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleare d. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special a ttention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 4? ???i? 01? ? 011 rev. 1.00 43 ???i? 01? ? 011 wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the "halt" instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after hto is "1". at this time, the lxt oscillator may not be stability if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the first instruction is executed. if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is "1", the system clock can be switched to the lxt or lirc oscillator after wake up. there are peripheral functions, such as wdt, tms and sim, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change accordingly. the on/off condition of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub .
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 4? ???i? 01? ? 011 rev. 1.00 43 ???i? 01? ? 011 watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f s , which is in turn supplied by one of two sources selected by confguration option: f sub or f sys /4. the f sub clock can be sourced from either the lxt or lirc oscillators, again chosen via a confguration option. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. the lxt oscillator is supplied by an external 32.768khz crystal. the other watchdog timer clock source option is the f sys /4 clock. the watchdog timer clock source can originate from its own internal lirc oscillator, the lxt oscillator or f sys /4. it is divided by a value of 28 to 215, using the ws2~ws0 bits in the wdtc register to obtain the required watchdog timer time-out period. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. this register together with several confguration options control the overall operation of the watchdog timer. wdtc register bit 7 6 5 4 3 ? 1 0 name fsyson ws? ws1 ws0 wdten3 wdten? wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 1 1 1 0 1 0 bit 7 fsyso : f sys control in idle mode 0: disable 1: enable bit 6 ~ 4 s2 s1 s0 : wdt time-out period selection 000: 256/f s 001: 512/f s 010: 1024/f s 011: 2048/f s 100: 4096/f s 101: 8192/f s 110: 16384/f s 111: 32768/f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period. bit 3 ~ 0 de3 de2 de1 de0 : wdt software control 1010: disable other: enable
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 44 ???i? 01? ? 011 rev. 1.00 45 ???i? 01? ? 011 watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. some of the watchdog timer options, such as enable/disable, clock source selection and clear instruction type are selected using confguration options. in addition to a confguration option to enable/disable the watchdog timer, there are also four bits, wdten3~wdten0, in the wdtc register to offer an additional enable/disable control of the watchdog timer. to disable the watchdog timer, as well as the confguration option being set to disable, the wdten3~wdten0 bits must also be set to a specifc value of "1010". any other values for these bits will keep the watchdog timer enabled, irrespective of the confguration enable/disable setting. after power on these bits will have the value of 1010. if the watchdog timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity. note that if the watchdog timer has been disabled, then any instruction relating to its operation will result in no operation. wdt confguration option wdten3~wdten0 bits wdt wdt enab ?e xxxx enab?e wdt disab ?e exce?t 1010 enab?e wdt disab ?e 1010 disab?e watchdog timer enable/disable control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the frst is an external hardware reset, which means a low level on the res pin, the second is using the watchdog timer software clear instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by confguration option. the frst option is to use the single "clr wdt" instruction while the second is to use the two commands "clr wdt1" and "clr wdt2". for the frst option, a simple execution of clr wdt will clear the wdt while for the second option, both "clr wdt1" and "clr wdt2" must both be executed alternately to successfully clear the watchdog timer. note that for this second option, if "clr wdt1" is used to clear the watchdog timer, successive executions of this instruction will have no effect, only the execution of a "clr wdt2" instruction will clear the watchdog timer. similarly after the "clr wdt2" instruction has been executed, only a successive "clr wdt1" instruction can clear the watchdog timer. the maximum time out period is when the 2 15 division ratio is selected. as an example, with a 32.768khz lxt oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. if the f sys /4 clock is used as the watchdog timer clock source, it should be noted that when the system enters the sleep or idle0 mode, then the instruction clock is stopped and the watchdog timer may lose its protecting purposes. for systems that operate in noisy environments, using the f sub clock source is strongly recommended.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 44 ???i? 01? ? 011 rev. 1.00 45 ???i? 01? ? 011

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? ? ? ? -? -? ?? ? ? ? ? ? ? ? ? ? ?? ? watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=100ms power-on reset timing chart
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 46 ???i? 01? ? 011 rev. 1.00 47 ???i? 01? ? 011 res pin as the reset pin is sha red with pb.0, the reset function must be selected using a confguration option. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. external res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. note: t rstd is power-on delay, typical time=100ms res reset timing chart
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 46 ???i? 01? ? 011 rev. 1.00 47 ???i? 01? ? 011 low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed t lvr , the lvr will ignore it and will not perform a reset function. one of a range of specifed voltage values for v lvr can be selected using confguration options. note: t rstd is power-on delay, typical time=100ms low voltage reset timing chart watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out fag to will be set to "1". note: t rstd is power-on delay, typical time=100ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to "0" and the to fag will be set to "1". refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 48 ???i? 01? ? 011 rev. 1.00 49 ???i? 01? ? 011 reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 powe?-on ?eset u u res o? lvr ?eset du?ing norm? l o? slow mode o?e?ation 1 u wdt time-out ?eset du?ing norm? l o? slow mode o?e?ation 1 1 wdt time-out ?eset du?ing idle o? sleep mode o?e?ation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p?og?am counte? reset to ze?o inte??u?ts ??? inte??u?ts wi?? be disab?ed wdt c?ea? afte? ?eset? wdt begins counting time ?/event counte? time ? counte? wi?? be tu? ned off in?ut/out?ut po?ts i/o ?o?ts wi?? be setu? as in?uts? and ?n0~? n11 in as ?/d in?ut ?in. stack pointe? stack pointe? wi?? ?oint to the to? of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. HT83F22 register register reset (power on) res or lvr reset wdt timeCout (normal operation) wdt timeCout (idle/sleep) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp CCCC CC00 CCCC CC00 CCCC CC00 CCCC CC00 ?cc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp CCCC xxxx CCCC uuuu CCCC uuuu CCCC uuuu st ? tus CC00 xxxx CCuu uuuu CC1u uuuu CC11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu integ CCCC 0000 CCCC 0000 CCCC 0000 CCCC uuuu lvdc CC00 C000 CC00 C000 CC00 C000 CCuu Cuuu intc0 C000 0000 C000 0000 C000 0000 Cuuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc? 0000 0000 0000 0000 0000 0000 uuuu uuuu intc3 CCC0 CCC0 CCC0 CCC0 CCC0 CCC0 CCCu CCCu mfi0 CC00 CC00 CC00 CC00 CC00 CC00 CCuu CCuu
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 48 ???i? 01? ? 011 rev. 1.00 49 ???i? 01? ? 011 register reset (power on) res or lvr reset wdt timeCout (normal operation) wdt timeCout (idle/sleep) mfi1 C000 C000 C000 C000 C000 C000 Cuuu Cuuu mfi? CC00 CC00 CC00 CC00 CC00 CC00 CCuu CCuu p? 1111 1111 1111 1111 1111 1111 uuuu uuuu p? c 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu ?drl xxxx CCCC xxxx CCCC xxxx CCCC (?drfs=0) uuuu CCCC (?drfs=1) uuuu uuuu ?drh xxxx xxxx xxxx xxxx xxxx xxxx (?drfs=0) uuuu uuuu (?drfs=1) CCCC uuuu ?dcr0 0110 C000 0110 C000 0110 C000 uuuu Cuuu ?dcr1 00C0 C000 00C0 C000 00C0 C000 uuCu Cuuu ?cer 1111 1111 1111 1111 1111 1111 uuuu uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 C111 0011 C111 0011 C111 uuuu Cuuu sim0c0 1110 000C 1110 000C 1110 000C uuuu uuuC sim0c1 1000 0001 1000 0001 1000 0001 uuuu uuuu sim0d xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sim0?/sim0c? 0000 0000 0000 0000 0000 0000 uuuu uuuu sim1c0 1110 000C 1110 000C 1110 000C uuuu uuuC sim1c1 1000 0001 1000 0001 1000 0001 uuuu uuuu sim1d xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sim1?/sim1c? 0000 0000 0000 0000 0000 0000 uuuu uuuu p? wu 0000 0000 0000 0000 0000 0000 uuuu uuuu p ?pu 0000 0000 0000 0000 0000 0000 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu cpc 1000 0CC1 1000 0CC1 1000 0CC1 uuuu uCCu tmpc0 1001 CC01 1001 CC01 1001 CC01 uuuu CCuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh CCCC CC00 CCCC CC00 CCCC CC00 CCCC CCuu tm0?l 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0?h CCCC CC00 CCCC CC00 CCCC CC00 CCCC CCuu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c? 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh CCCC CC00 CCCC CC00 CCCC CC00 CCCC CCuu tm1?l 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1?h CCCC CC00 CCCC CC00 CCCC CC00 CCCC CCuu
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 50 ???i? 01? ? 011 rev. 1.00 51 ???i? 01? ? 011 register reset (power on) res or lvr reset wdt timeCout (normal operation) wdt timeCout (idle/sleep) tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh CCCC CC00 CCCC CC00 CCCC CC00 CCCC CCuu tmr 0000 0000 0000 0000 0000 0000 uuuu uuuu tmrc 00C0 1000 00C0 1000 00C0 1000 uuCu uuuu misc 000C CC0C 000C CC0C 000C CC0C uuuC CCuC d?l xxxx CCCC uuuu CCCC uuuu CCCC uuuu CCCC d?h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu vol xxxC CCCC uuuC CCCC uuuC CCCC uuuC CCCC scomc 0000 0000 0000 0000 0000 0000 uuuu uuuu ?gcc 000C C000 000C C000 000C C000 uuuC Cuuu note: * stands for warm reset, C not implement u stands for unchanged x stands for unknown input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa~pc these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list register name bit 7 6 5 4 3 2 1 0 p? wu d7 d6 d5 d4 d3 d? d1 d0 p ?pu d7 d6 d5 d4 d3 d? d1 d0 p? d7 d6 d5 d4 d3 d? d1 d0 p? c d7 d6 d5 d4 d3 d? d1 d0 pbpu d7 d6 d5 d4 d3 d? d1 d0 pb d7 d6 d5 d4 d3 d? d1 d0 pbc d7 d6 d5 d4 d3 d? d1 d0 pcpu d7 d6 d5 d4 d3 d? d1 d0 pc d7 d6 d5 d4 d3 d? d1 d0 pcc d7 d6 d5 d4 d3 d? d1 d0
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 50 ???i? 01? ? 011 rev. 1.00 51 ???i? 01? ? 011 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu~pcpu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pbpu register bit 7 6 5 4 3 ? 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pcpu register bit 7 6 5 4 3 ? 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o port bit 7 ~ bit 0 pull-high control 0: disable 1: enable port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 p u : port a bit 7 ~ bit 0 wake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as pac~pcc, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0,
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 5? ???i? 01? ? 011 rev. 1.00 53 ???i? 01? ? 011 the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pbc register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pcc register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 i/o port bit 7 ~ bit 0 input/output control 0: output 1: input i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac~pcc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa~pc, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 5? ???i? 01? ? 011 rev. 1.00 53 ???i? 01? ? 011

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HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 54 ???i? 01? ? 011 rev. 1.00 55 ???i? 01? ? 011 timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions each device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either two or three individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact and enhanced tm sections. introduction the device contains two tms, each tm having a reference name of tm0 and tm1. each individual tm can be categorised as a certain type, namely compact type tm, or enhanced type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact and enhanced tms will be described in this section, the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the two types of tms are summarised in the accompanying table. function ctm etm time ?/counte? v v i/p ca ?tu?e v com?a?e match out?ut v v pwm channe?s 1 ? sing?e pu?se out?ut 1 pwm ??ignment edge edge & cent?e pwm ?djustment pe?iod & duty duty o? pe?iod duty o? pe?iod tm function summary this device contains a compact type and an enhanced type tm which are shown in the table together with their individual reference name, tm0~tm1. tm0 tm1 10-bit ctm 10-bit etm tm name/type reference tm operation the two different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understand how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 54 ???i? 01? ? 011 rev. 1.00 55 ???i? 01? ? 011 tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock fh, the ftbc clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact type tm has two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have one or more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and device is different, the details are provided in the accompanying table. ctm etm registers tp0_0? tp0_1 tp1?? tp1b_0? tp1b_1? tp1b_? tmpc0 tm output pins
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 56 ???i? 01? ? 011 rev. 1.00 57 ???i? 01? ? 011 tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared function, is implemented using one register, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers bit 7 6 5 4 3 2 1 0 tmpc0 t1?cp0 t1bcp? t1bcp1 t1bcp0 t0cp1 t0cp0 tm input/output pin control registers list

tm0 function pin control block diagram
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 56 ???i? 01? ? 011 rev. 1.00 57 ???i? 01? ? 011

tm1 function pin control block diagram
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 58 ???i? 01? ? 011 rev. 1.00 59 ???i? 01? ? 011 bit 7 6 5 4 3 2 1 0 name t1?cp0 t1bcp? t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w por 1 0 0 1 0 1 bit 7 1cp0 : tp1a pin control 0: disable 1: enable bit 6 1bcp2 : tp1b_2 pin control 0: disable 1: enable bit 5 1bcp1 : tp1b_1 pin control 0: disable 1: enable bit 4 1bcp0 : tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as "0" bit 1 0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 0cp0 : tp0_0 pin control 0: disable 1: enable programming considerations the tm counter registers and the capture/compare ccra registers, being 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra register is implemented in the way shown in the following diagram and accessing this register is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra low byte register, named tmxal, in the following access procedures. accessing the ccra low byte register without following the access procedures will result in unpredictable value. data bus 8-bit buffer tmxdh tmxdl tmxah tmxal tm counter register (read only) tm ccra register (read/write)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 58 ???i? 01? ? 011 rev. 1.00 59 ???i? 01? ? 011 the following steps show the read and write procedures: writing data to ccra ? step 1. write data to low byte tmxal C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte tmxah C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. reading data from the counter registers and ccra ? step 1. read data from the high byte tmxdh, tmxah C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal C this step reads data from the 8-bit buffer. compact type tm although the simplest form of the tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one or two external output pins. these two external output pins can be the same signal or the inverse signal. name tm no. tm input pin tm output pin 10-bit ctm 0 tck0 tp0_0? tp0_1
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? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? compact type tm block diagram compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 60 ???i? 01? ? 011 rev. 1.00 61 ???i? 01? ? 011 compact type tm register description overall operation of the compact tm is controlled using six registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm0c0 t0p ?u t0ck? t0ck1 t0ck0 t0on t0rp? t0rp1 t0rp0 tm0c1 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr tm0dl d7 d6 d5 d4 d3 d? d1 d0 tm0dh d9 d8 tm0?l d7 d6 d5 d4 d3 d? d1 d0 tm0?h d9 d8 compact tm register list (if ctm is tm0) tm0dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 m0d : tm0 counter low byte register bit 7 ~ bit 0 tm0 10-bit counter bit 7 ~ bit 0 tm0dh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as " 0 " bit 1~0 m0dh : tm0 counter high byte register bit 1 ~ bit 0 tm0 10-bit counter bit 9 ~ bit 8 tm0al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 m0 : tm0 ccra low byte register bit 7 ~ bit 0 tm0 10-bit ccra bit 7 ~ bit 0 tm0ah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 m0h : tm0 ccra high byte register bit 1 ~ bit 0 tm0 10-bit ccra bit 9 ~ bit 8
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 60 ???i? 01? ? 011 rev. 1.00 61 ???i? 01? ? 011 tm0c0 register bit 7 6 5 4 3 2 1 0 name t0p ?u t0ck? t0ck1 t0ck0 t0on t0rp? t0rp1 t0rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 0pu : tm0 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 0c2~0c0 : select tm0 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 0o : tm0 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t0oc bit, when the t0on bit changes from low to high. bit 2~0 0rp2~0rp0 : tm0 ccrp 3-bit register, compared with the tm0 counter bit 9~bit 7 comparator p match period 000: 1024 tm0 clocks 001: 128 tm0 clocks 010: 256 tm0 clocks 011: 384 tm0 clocks 100: 512 tm0 clocks 101: 640 tm0 clocks 110: 768 tm0 clocks 111: 896 tm0 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counters highest three bits. the result of this comparison can be selected to clear the internal counter if the t0cclr bit is set to zero. setting the t0cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 6? ???i? 01? ? 011 rev. 1.00 63 ???i? 01? ? 011 tm0c1 register bit 7 6 5 4 3 2 1 0 name t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 0m1~0m0 : select tm0 operating mode 00: compare match output mode 01: undefned mode 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t0m1 and t0m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 0io1~0io0 : select tp0_0, tp0_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: force inactive state 01: force active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t0oc bit in the tm0c1 register. note that the output level requested by the t0io1 and t0io0 bits must be different from the initial value setup using the t0oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t0on bit from low to high. bit 3 0oc : tp0_0, tp0_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 6? ???i? 01? ? 011 rev. 1.00 63 ???i? 01? ? 011 bit 2 t0pol : tp0_0, tp0_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp0_0 or tp0_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t0dpx : tm0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t0cclr : select tm0 counter clear condition 0: tm0 comparatror p match 1: tm0 comparatror a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t0cclr bit is not used in the pwm mode. the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 64 ???i? 01? ? 011 rev. 1.00 65 ???i? 01? ? 011 ccr? ccrp 0x3ff counte ? ove ? f ? ow ccr? int. f ? ag tn ? f ccrp int. f ? ag tnpf ccrp > 0 counte ? c ? ea? ed by ccrp va ? ue tpn ? o/p pin tnon bit pause counte ? reset out ? ut pin set to initia ? leve ? low if tnoc = 0 out ? ut togg? e with tn ?f f? ag he ? e tnio1 ? tnio0 = 11 togg ? e out ? ut se? ect now tnio1 ? tnio0 = 10 ? ctive high out ? ut se ? ect out ? ut not affected by tn ?f f ? ag. remains high unti ? ? eset by tnon bit tncclr = 0; tn ? m1 ? tn ? m0 = 00 tnp ?u bit resume sto ? time ccrp > 0 ccrp = 0 tn ? pol bit out ? ut pin reset to initia ? va ? ue out ? ut inve? ts when tnpol is high out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function counte ? va ? ue compare match output mode tncclr = 0 note: 1. with tncclr = 0 the comparator p match will clear the counter 2. tm output pin controlled only by tnaf fag 3. output pin reset to initial state by tnon bit rising edge ccrp ccr? 0x3ff ccr? = 0 counte ? ove ? f ? ows ccrp int. f ? ag tnpf ccr? int. f ? ag tn ? f ccr ? > 0 counte ? c ? ea? ed by ccr ? va ? ue tm o/p pin tnon bit pause counte ? reset out ? ut pin reset to initia ? va ? ue out ? ut pin set to initia ? leve ? low if tnoc = 0 out ? ut togg? e with tn ?f f? ag he ? e tnio1 ? tnio0 = 11 togg ? e out ? ut se? ect now tnio1 ? tnio0 = 10 ? ctive high out ? ut se ? ect tnp ?u bit resume sto ? time tnpf not gene? ated no tn ?f f? ag gene? ated on ccr ? ove ? f ? ow out ? ut does not change ccr? = 0 out ? ut inve? ts when tnpol is high tnpol bit tncclr = 1; tnm1 ? tnm0 = 00 out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function out ? ut not affected by tn ?f f ? ag ? emains high unti ? ? eset by tnon bit counte ? va ? ue compare match output mode tncclr = 1 note: 1. with tncclr = 1 the comparator a match will clear the counter 2. tm output pin controlled only by tnaf fag 3.tm output pin reset to initial state by tnon rising edge 4. tnpf fags not generated when tncclr = 1
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 64 ???i? 01? ? 011 rev. 1.00 65 ???i? 01? ? 011 timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the val ues in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 66 ???i? 01? ? 011 rev. 1.00 67 ???i? 01? ? 011 ccrp ccr? counte ? va ? ue counte ? c ? ea? ed by ccrp ccr? int. f ? ag tn ? f ccrp int. f ? ag tnpf pwm out ?ut tm pin tnoc = 1 tnon bit pwm duty cyc ? e set by ccr ? pwm pe ? iod set by ccrp tnio1 ? tnio0 = 10 pwm out ?ut tnio1 ? tnio0 = 00 out ? ut inactive tnio1 ? tnio0 = 10 inte ?? u ? ts sti ?? gene? ated he ? e tnio1 ? tnio0 = 00 out ? ut fo? ced to inactive ? eve ? but pwm function kee ? s ? unning inte ? na ?? y tnio1 ? tnio0 = 10 resume pwm out ? ut counte ? sto ? if tnon bit ? ow counte ? ? eset when tnon ? etu ? ns high pwm ? esumes o?e? ation time tnpol bit out ? ut inve ? ts when tnpol = 1 tm pin tnoc = 0 tnp ?u bit resume pause tndpx = 0; tnm1 ? tnm0 = 10 out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function pwm mode tndpx = 0 note: 1. here tndpx = 0 - counter cleared by ccrp 2. counter clear sets pwm period 3. internal pwm function continues even when tnio1, tnio0 = 00 or 01 4. tncclr bit has no infuence on pwm operation ccr? ccrp counte ? va ? ue counte ? c ? ea? ed by ccr ? ccrp int. f ? ag tnpf ccr? int. f ? ag tn ? f tnon bit pwm duty cyc ? e set by ccrp pwm pe ? iod set by ccr ? tnio1 ? tnio0 = 10 pwm out ?ut tnio1 ? tnio0 = 00 out ? ut inactive tnio1 ? tnio0 = 10 inte ?? u ? ts sti ?? gene? ated he ? e tnio1 ? tnio0 = 00 out ? ut fo? ced to inactive ? eve ? but pwm function kee ? s ? unning inte ? na ?? y tnio1 ? tnio0 = 10 resume pwm out ? ut counte ? sto ? if tnon bit ? ow counte ? ? eset when tnon ? etu ? ns high pwm ? esumes o?e? ation time tnpol bit out ? ut inve ? ts when tnpol = 1 tm pin tnoc = 0 tnp ?u bit resume pause tndpx = 1; tnm1 ? tnm0 = 10 out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function pwm mode tndpx = 1 note: 1. here tndpx = 1 - counter cleared by ccra 2. counter clear sets pwm period 3. internal pwm function continues even when tnio1, tnio0 = 00 or 01 4. tncclr bit has no infuence on pwm operation
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 66 ???i? 01? ? 011 rev. 1.00 67 ???i? 01? ? 011 enhanced type tm C etm the enhanced type tm contains five operating modes, which are compare match output, timer/event counter, capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three or four external output pins. ctm name tm no. tm input pin tm output pin ht83f?? 10-bit etm 1 tck1 tp1?? tp1b_0? tp1b_1? tp1b_? enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. there are three internal comparators with the names, comparator a, comparator b and comparator p. these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore compared with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers.
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HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 68 ???i? 01? ? 011 rev. 1.00 69 ???i? 01? ? 011 enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1p ?u t1ck? t1ck1 t1ck0 t1on t1rp? t1rp1 t1rp0 tm1c1 t1?m1 t1?m0 t1?io1 t1?io0 t1?oc t1?pol t1cdn t1cclr tm1c? t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 tm1dl d7 d6 d5 d4 d3 d? d1 d0 tm1dh d9 d8 tm1?l d7 d6 d5 d4 d3 d? d1 d0 tm1?h d9 d8 tm1bl d7 d6 d5 d4 d3 d? d1 d0 tm1bh d9 d8 10-bit enhanced tm register list (if etm is tm1) 10-bit enhanced tm register list tm1c0 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1p ?u t1ck? t1ck1 t1ck0 t1on t1rp? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 1pu : tm1 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 1c2~1c0 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 1o : tm1 counter on/off control 0: off 1: on
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 68 ???i? 01? ? 011 rev. 1.00 69 ???i? 01? ? 011 this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tm1c1 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1?m1 t1?m0 t1?io1 t1?io0 t1?oc t1?pol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1am1~t1am0 : select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1am1 and t1am0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0 : select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/ single pulse output mode 00: force inactive state 01: force active state 10: pwm output 11: single pulse output
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 70 ???i? 01? ? 011 rev. 1.00 71 ???i? 01? ? 011 capture input mode 00: input capture at rising edge of tp1a 01: input capture at falling edge of tp1a 10: input capture at falling/rising edge of tp1a 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register. note that the output level requested by the t1aio1 and t1aio0 bits must be different from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. bit 3 t1aoc : tp1a output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol : tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1cdn : tm1 counter count up or down fag 0: count up 1: count down bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to select the method which clears the counter. remember that the enhanced tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 70 ???i? 01? ? 011 rev. 1.00 71 ???i? 01? ? 011 tm1c2 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 1bm1~1bm0 : select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1bm1 and t1bm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 1bio1~1bio0 : select tp1b_0, tp1b_1, tp1b_2 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: force inactive state 01: force active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling edge of tp1b_0, tp1b_1, tp1b_2 10: input capture at falling/rising edge of tp1b_0, tp1b_1, tp1b_2 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register. note that the output level requested by the t1bio1 and t1bio0 bits must be different from the initial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. bit 3 1boc : tp1b_0, tp1b_1, tp1b_2 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 7? ???i? 01? ? 011 rev. 1.00 73 ???i? 01? ? 011 this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol : tp1b_0, tp1b_1, tb1b_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1, tp1b_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1~0 t1pwm1~t1pwm0 : select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down tm1dl register C 10-bit etm name d7 d6 d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register C 10-bit etm name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as " 0" ? bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm1al register C 10-bit etm name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al : tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 tm1ah register C 10-bit etm name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, bit 1~0 tm1ah : tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 7? ???i? 01? ? 011 rev. 1.00 73 ???i? 01? ? 011 tm1bl register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 m1b : tm1 ccrb low byte register bit 7~bit 0 tm1 10-bit ccrb bit 7~bit 0 tm1bh register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, bit 1~0 m1bh : tm1 ccrb high byte register bit 1~bit 0 tm1 10-bit ccrb bit 9 ~ bit 8 enhanced type tm operating modes the enhanced type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register. etm operating mode ccra compare match output mode ccra timer/ counter mode ccra pwm output mode ccra single pulse output mode ccra input capture mode ccrb com?a?e match out?ut mode ccrb time ?/ counte? mode ccrb pwm out?ut mode ccrb sing?e pu?se out?ut mode ccrb in?ut ca?tu?e mode
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 74 ???i? 01? ? 011 rev. 1.00 75 ???i? 01? ? 011 compare output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all cleared to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both the tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf or tnbf interrupt request fag is generated after a compare match occurs from comparator a or comparator b. the tnpf interrupt request flag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the tnaio1, tnaio0 bits (for the tpna pin) and tnbio1, tnbio0 bits (for the tpnb_0, tpnb_1 or tpnb_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparator b. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnaoc or tnboc bit for tpna or tpnb_0, tpnb_1, tpnb_2 output pins. note that if the tnaio1,tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place. ccr? ccrp 0x3ff counte ? ove ? f ? ow ccr? int. f ? ag tn ? f ccrp int. f ? ag tnpf ccrp > 0 counte ? c ? ea? ed by ccrp va ? ue tpn ? o/p pin tnon bit pause counte ? reset out ? ut pin set to initia ? leve ? low if tnoc = 0 out ? ut togg? e with tn ?f f? ag he ? e tnio1 ? tnio0 = 11 togg ? e out ? ut se? ect now tnio1 ? tnio0 = 10 ? ctive high out ? ut se ? ect out ? ut not affected by tn ?f f ? ag. remains high unti ? ? eset by tnon bit tncclr = 0; tn ? m1 ? tn ? m0 = 00 tnp ?u bit resume sto ? time ccrp > 0 ccrp = 0 tn ? pol bit out ? ut pin reset to initia ? va ? ue out ? ut inve? ts when tnpol is high out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function counte ? va ? ue etm ccra compare match output mode tncclr = 0 note: 1. with tncclr = 0 the comparator p match will clear the counter 2. tpna output pin controlled only by tnaf fag 3. output pin reset to initial state by tnon bit rising edge
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 74 ???i? 01? ? 011 rev. 1.00 75 ???i? 01? ? 011 ccrb ccrp 0x3ff counte ? ove ? f ? ow ccrb int. f ? ag tnb ?f ccrp int. f ? ag tnpf ccrp > 0 counte ? c ? ea? ed by ccrp va ? ue tpnb o/p pin tnon bit pause counte ? reset out ? ut pin set to initia ? leve ? low if tnboc = 0 out ? ut togg? e with tnbf f? ag he ? e tnbio1 ? tnbio0 = 11 togg ? e out ? ut se? ect now tnbio1 ? tnbio0 = 10 ? ctive high out ? ut se? ect tncclr = 0; tnbm1 ? tnbm0 = 00 tnp ?u bit resume sto ? ccrp > 0 ccrp = 0 tnbpol bit out ? ut pin reset to initia ? va ? ue out ? ut inve? ts when tnbpol is high out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function out ? ut not affected by tnbf f ? ag. remains high unti ? ? eset by tnon bit counte ? va ? ue time etm ccrb compare match output mode tncclr = 0 note: 1. with tncclr = 0 the comparator p match will clear the counter 2. tpnb output pin controlled only by tnbf fag 3. output pin reset to initial state by tnon bit rising edge ccrb ccr? 0x3ff ccr? = 0 counte ? ove ? f ? ows ccrb int. f ? ag tnbf ccr? int. f ? ag tn ? f ccr ? > 0 counte ? c ? ea? ed by ccr ? va ? ue tpnb o/p pin tnon bit pause counte ? reset out ? ut pin set to initia ? leve ? low if tnboc = 0 out ? ut togg? e with tnbf f? ag he ? e tnbio1 ? tnbio0 = 11 togg ? e out ? ut se? ect now tnbio1 ? tnbio0 = 10 ? ctive high out ? ut se? ect tnp ?u bit resume sto ? time no tn ?f f? ag gene? ated on ccr ? ove ? f ? ow ccr? = 0 out ? ut inve? ts when tnbpol is high tnbpol bit tncclr = 1; tnbm1 ? tnbm0 = 00 out ? ut pin reset to initia ? va ? ue out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function out ? ut not affected by tnbf f ? ag ? emains high unti ? ? eset by tnon bit counte ? va ? ue etm ccrb compare match output mode tncclr = 1 note: 1. with tncclr = 1 the comparator a match will clear the counter 2. tpnb output pin controlled only by tnbf fag 3. tpnb output pin reset to initial state by tnon rising edge 4. tnpf fags not generated when tncclr = 1
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 76 ???i? 01? ? 011 rev. 1.00 77 ???i? 01? ? 011 timer/counter mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 register should all be set high. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is controlled. with the tncclr bit set high, the pwm period can be fnely controlled using the ccra registers. in this case the ccrb registers are used to set the pwm duty value (for tpnb output pins). the ccrp bits are not used and tpna output pin is not used. the pwm output can only be generated on the tpnb output pins. with the tncclr bit cleared to zero, the pwm period is set using one of the eight values of the three ccrp bits, in multiples of 128. now both ccra and ccrb registers can be used to setup different duty cycle values to provide dual pwm outputs on their relative tpna and tpnb pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is reset to zero. with all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. interrupt fags, one for each of the ccra, ccrb and ccrp, will be generated when a compare match occurs from either the comparator a, comparator b or comparator p. the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform. etm, pwm mode, edge-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?56 384 51? 640 768 896 10?4 ? duty ccr? b duty ccrb
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 76 ???i? 01? ? 011 rev. 1.00 77 ???i? 01? ? 011 etm, pwm mode, edge-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 pe?iod 1 ? 3 511 51? 10?1 10?? 10?3 b duty ccrb etm, pwm mode, center-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod ?56 51? 768 10?4 1?80 1536 179? ?046 ? duty (ccr?x?) -1 b duty (ccrbx?) -1 etm, pwm mode, center-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 pe?iod ? 4 6 10?? 10?4 ?04? ?044 ?046 b duty (ccrb x ?) x 1 ccrp ccr? counte ? va ? ue counte ? c ? ea? ed by ccrp ccr? int. f ? ag tn ? f ccrp int. f ? ag tnpf tpn ? pin tn ? oc = 1 tnon bit duty cyc ? e set by ccr ? pwm pe ? iod set by ccrp tn ? io1 ? tn ? io0 = 10 pwm out ? ut tn ? io1 ? tn ? io0 = 00 out ? ut inactive tn ? io1 ? tn ? io0 = 10 inte ?? u? t sti ?? gene? ated he ? e tn ? io1 ? tn ? io0 = 00 out ? ut is inactive pwm ? uns inte ? na ?? y tn ? io1 ? tn ? io0 = 10 resume pwm out ? ut time tncclr = 0 ; mode bits tn ? (b)m1 ? tn ? (b)m0 = 10 tnpwm1/tnpwm0 = 00 tn ? pol bit out ? ut inve ? ts when tn ? pol = 1 tpnb pin tnboc = 0 tnp ?u bit resume pause ccrb ccrb int. f ? ag tnbf tpnb pin tnboc = 1 duty cyc ? e set by ccrb pwm ? esumes o?e? ation out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function counte ? sto ?s if tnon bit ? ow counte ? ? eset when tnon ? etu ? ns high pwm mode edge aligned note: 1. here tncclr = 0 therefore ccrp clears counter and determines pwm period 2. internal pwm function continues even when tnaio1, tnaio0 ( or tnbio1, tnbio0) = 00 or 01 3. ccra controls tpna pwm duty and ccrb controls tpnb pwm duty
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 78 ???i? 01? ? 011 rev. 1.00 79 ???i? 01? ? 011 ccr? counte ? va ? ue counte ? c ? ea? ed by ccr ? ccr? int. f ? ag tn ? f tnon bit pwm pe ? iod set by ccr ? tnbpol bit tpnb pin tnboc = 0 tnp ?u bit resume pause ccrb ccrb int. f ? ag tnbf tpnb pin tnboc = 1 duty cyc ? e set by ccrb out ? ut inve ? ts when tnbpol = 1 tncclr = 1 ; mode bits tn ? (b)m1 ? tn ? (b)m0 = 10 tnpwm1/tnpwm0 = 00 pwm ? esumes o?e? ation out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function time counte ? sto ?s if tnon bit ? ow counte ? ? eset when tnon ? etu ? ns high pwm mode edge aligned note: 1. here tncclr = 1 therefore ccra clears counter and determines pwm period 2. internal pwm function continues even when tnbio1, tnbio0 = 00 or 01 3. ccra controls tpnb pwm period and ccrb controls tpnb pwm duty ccrp ccr? ccr? int. f ? ag tn ? f ccrp int. f ? ag tnpf tpn ? pin tn ? oc = 1 tnon bit duty cyc ? e set by ccr ? pwm pe ? iod set by ccrp tn ? io1 ? tn ? io0 = 00 out ? ut inactive counte ? sto ?s if tnon bit ? ow counte ? ? eset when tnon ? etu ? ns high tn ? pol bit out ? ut inve ? ts when tn ? pol = 1 tpnb pin tnboc = 0 tnp ?u bit resume pause ccrb ccrb int. f ? ag tnbf tpnb pin tnboc = 1 duty cyc ? e set by ccrb tn ? io1 ? tn ? io0 = 10 pwm out ? ut tn ? io1 ? tn ? io0 = 10 pwm out ? ut counte ? va ? ue tncclr = 0; mode bits tn ? (b)m1 ? tn ? (b)m0 = 10 tnpwm1/tnpwm0 = 11 time pwm ? esumes o?e? ation out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function pwm mode centre aligned note: 1. here tncclr = 0 therefore ccrp clears counter and determines pwm period 2. tnpwm1/tnpwm0 = 11 therefore pwm is centre aligned 3. internal pwm function continues even when tnaio1, tnaio0 ( or tnbio1, tnbio0) = 00 or 01 4. ccra controls tpna pwm duty and ccrb controls tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 78 ???i? 01? ? 011 rev. 1.00 79 ???i? 01? ? 011 ccr? ccr? int. f ? ag tn ? f tnon bit pwm pe ? iod set by ccr ? time tnbpol bit out ? ut inve ? ts when tnbpol = 1 tpnb pin tnboc = 0 tnp ?u bit resume pause ccrb ccrb int. f ? ag tnbf tpnb pin tnboc = 1 duty cyc ? e set by ccrb counte ? va ? ue tncclr = 1; mode bits tn ? (b)m1 ? tn ? (b)m0 = 10 tnpwm1/tnpwm0 = 11 pwm ? esumes o?e? ation out ? ut cont ? o ?? ed by othe ? ? in - sha ? ed function counte ? sto ?s if tnon bit ? ow counte ? ? eset when tnon ? etu ? ns high pwm mode centre aligned note: 1. here tncclr = 1 therefore ccra clears counter and determines pwm period 2. tnpwm1/tnpwm0 = 11 therefore pwm is centre aligned 3. internal pwm function continues even when tnbio1, tnbio0 = 00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value. single pulse output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. the trigger for the pulse tpnb output leading edge is a compare match from comparator b, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb. in this way the ccra value can be used to control the pulse width of tpna. the ccra-ccrb value can be used to control the pulse width of tpnb. a compare match from comparator a and comparator b will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 80 ???i? 01? ? 011 rev. 1.00 81 ???i? 01? ? 011

? ? ? ? ? ? ? ? ? ?? ? ? ? ? - ? ? ? - ? ?? single pulse generation ccr? ccrb counte ? va ? ue counte ? sto ?? ed by ccr ? ccrb int. f ? ag tnbf ccr? int. f ? ag tn ? f tpn ? pin tn ? oc = 1 tnon bit tn ? io1 ? tn ? io0 and tnbio1 ? tnbio0 = 11 sing ? e pu ? se out ? ut tn ? io1 ? tn ? io0 and tnbio1 ? tnbio0 = 00 out ? ut inactive tn ? io1 ? tn ? io0 and tnbio1 ? tnbio0 = 11 he ? e tn ? io1 ? tn ? io0 and tnbio1 ? tnbio0 = 00 out ? ut fo? ced to inactive ? eve ? but counte ? kee ? s ? unning inte ? na ?? y tn ? io1 ? tn ? io0 and tnbio1 ? tnbio0 = 11 resume sing ? e pu ? se out ?ut counte ? sto ?s by softwa ? e counte ? ? eset when tnon ? etu ? ns high time tn ? pol ? tnbpol bit out ? ut inve ? ts when tn ? pol = 1 tpn ? pin tn ? oc = 0 tnp ?u bit resume pause softwa ? e t ? igge ? tckn ? in c ? ea? ed by ccr ? match tckn ? in t ? igge ? ? uto. set by tckn ? in softwa ? e c ? ea? softwa ? e t ? igge ? softwa ? e t ? igge ? tn ? m1? tn ? m0 and tnbm1 ? tnbm0 = 10; tn ? io1 ? tn ? io0 and tnbio1 ? tnbio0 = 11 tpnb pin tnboc = 1 pu ? se width set by ccr ? tpnb pin tnboc = 0 pu ? se width set by ccr ? - ccrb out ? ut inve ? ts when tnbpol = 1 etm single pulse mode
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 80 ???i? 01? ? 011 rev. 1.00 81 ???i? 01? ? 011 capture input mode to select this mode bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tmnc1 and tmnc2 registers. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irrespective of what events occur on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnaio1, tnaio0 and tnbio1, tnbio0 bits can select the active trigger edge on the tpna and tpnb_0, tpnb_1, tpnb_2 pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, however it must be noted that the counter will continue to run. as the tpna and tpnb_0, tpnb_1, tpnb_2 pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are not used in this mode. ccrp counte ? ove ? f ? ow ccrp int. f ? ag tnpf ccr? int. f ? ag tn ? f tnon bit pause counte ? reset tnp ?u bit resume sto ? time yy xx ccr? va ? ue xx tm ca ? tu? e pin yy tn ? io1 ? tn ? io0 va ? ue 00 - rising edge 01 - fa ?? ing edge 11 - disab ? e ca ? tu? e ? ctive edge ? ctive edge xx 10 - both edges ? ctive edges yy tn ? m1 ? tn ? m0 = 01 counte ? va ? ue etm ccra capture input mode note: 1. tnam1, tnam0 = 01 and active edge set by tnaio1 and tnaio0 bits 2. tm capture input pin active edge transfers counter value to ccra 3. tncclr bit not used 4. no output function - tnaoc and tnapol bits not used 5. ccrp sets counter maximum value
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 8? ???i? 01? ? 011 rev. 1.00 83 ???i? 01? ? 011 ccrp counte ? ove ? f ? ow ccrp int. f ? ag tnpf ccrb int. f ? ag tnbf tnon bit pause counte ? reset tnp ?u bit resume sto ? yy xx ccrb va ? ue xx tm ca ? tu? e pin yy tnbio1 ? tnbio0 va ? ue 00 - rising edge 01 - fa ?? ing edge 11 - disab ? e ca ? tu? e ? ctive edge ? ctive edge xx 10 - both edges ? ctive edges yy tnbm1 ? tnbm0 = 01 time counte ? va ? ue etm ccrb capture input mode note: 1. tnbm1, tnbm0 = 01 and active edge set by tnbio1 and tnbio0 bits 2. tm capture input pin active edge transfers counter value to ccrb 3. tncclr bit not used 4. no output function - tnboc and tnbpol bits not used 5. ccrp sets counter maximum value timer/event counter C tmr in addition to the timer modules, the device provides an additional count-up timer/event counter of 8-bit capacity with the name tmr. it should not be confused with the timer modules as its structure and operation is very different from that of the timer modules. one specifc purpose of this timer is for the scf clock. as the timer has three different operating modes, it can be confgured to operate as a general timer, an external event counter or as a pulse width capture device. the provision of an internal prescaler to the clock circuitry gives added range to the timer . there are two types of registers related to the timer/event counter. the first is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defnes the timer options and determines how the timer is to be used. the device can have the timer clock confgured to come from the internal clock source. in addition, the timer clock source can also be confgured to come from an external timer pin. confguring the timer/event counter input clock source the timer/event counter clock source can originate from various sources, an internal clock or an external pin. the internal clock source is used when the timer is in the timer mode or in the pulse width capture mode. this internal clock source is first divided by a prescaler, the division ratio of which is conditioned by the timer control register bits tpsc0~tpsc2 and the internal clock source is from f sys . an external clock source is used when the timer/event counter is in the event counting mode, the clock source being provided on an external timer pin. depending upon the condition of the teg bit, each high to low, or low to high transition on the external timer pin will increment the counter by one.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 8? ???i? 01? ? 011 rev. 1.00 83 ???i? 01? ? 011 timer register C tmr the timer register is special function register located in the special purpose data memory and is the place where the actual timer value is stored. this register is known as tmr. the value in the timer register increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh at which point the timer overfows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and continue counting. note that to achieve a maximum full range count of ffh, the preload register must frst be cleared to all zeros. it should be noted that after power-on, the preload registers will be in an unknown condition. note that if the timer/event counter is in an off condition and data is written to its preload register, this data will be immediately written into the actual counter. however, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overfow occurs. timer control register C tmrc the fexible features of the holtek microcontroller timer/event counter enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. the timer control register is known as tmrc. it is the timer control register together with its corresponding timer register that controls the full operation of the timer/event counter. before the timer can be used, it is essential that the timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width capture mode, bits 7 and 6 of the timer control register, which are known as the bit pair tmr1/tmr0, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as ton, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. bits 0~2 of the timer control register determine the division ratio of the input clock prescaler. the prescaler bit settings have no effect if an external clock source is used. if the timer is in the event count or pulse width capture mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as teg.
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? - clock structure for tmr
? ? ? ? ? ? - ? ? ? tmr structure
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 84 ???i? 01? ? 011 rev. 1.00 85 ???i? 01? ? 011 tmrc register bit 7 6 5 4 3 2 1 0 name tmr1 tmr0 ton teg tpsc? tpsc1 tpsc0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 0 0 0 bit 7, 6 tmr1, tmr0 : timer /event counter operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 unimplemented, read as 0 ton : timer/event counter counting enable 0: disable 1: enable teg : event counter active edge selection 0: count on rising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rising edge 1: start counting on rising edge, stop on falling edge tpsc2, tpsc1, tpsc0 : timer prescaler rate selection timer internal clock = sys /2 sys /4 sys /8 sys /16 sys /32 sys /64 sys /128 sys /256
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 84 ???i? 01? ? 011 rev. 1.00 85 ???i? 01? ? 011 timer mode in this mode, the timer/event counter can be utilised to measure fxed time intervals, providing an internal interrupt signal each time the timer/event counter overfows. to operate in this mode, the operating mode select bit pair, tmr1/tmr0, in the timer/event counter control register must be set to the correct value as shown. cont?o? registe? o?e?ating mode bit7 bit6 se?ect bits fo? the time? mode 1 0 in this mode the internal clock is used as the timer clock. the timer input clock source is from f sys . however, this timer clock source is further divided by a prescaler, the value of which is determined by the bits tpsc2~tpsc0 in the timer control register. the timer-on bit, ton must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overfows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. a timer overfow condition and corresponding internal interrupt is one of the wake-up sources. note that one main reason for tmr is as a clock source for the internal scf. in order to obtain a precise clock source for the scf, the timer/event counter interrupt should be disabld to prevent erroneous operation. refer to the scf section for more details.
timer mode timing chart event counter mode in this mode, a number of externally changing logic events, occurring on the external timer tmr pin, can be recorded by the timer/event counter. to operate in this mode, the operating mode select bit pair, tmr1/tmr0, in the timer control register must be set to the correct value as shown. cont?o? registe? o?e?ating mode bit7 bit6 se?ect bits fo? the event counte? mode 0 1 in this mode, the external timer tmr pin is used as the timer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, teg, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the teg is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register is reset to zero. as the external timer pin is shared with an i/o pin, to ensure that the pin is confgured to operate as an event counter input pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register confgures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the idle/sleep mode, the timer/event counter will continue to record externally changing logic events on the timer input tmr pin. as a result w hen the timer overfows it will generate a timer interrupt and corresponding wake-up source.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 86 ???i? 01? ? 011 rev. 1.00 87 ???i? 01? ? 011
enent counter mode timing chart (teg=1) pulse width capture mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. to operate in this mode, the operating mode select bit pair, tmr1/tmr0, in the timer control register must be set to the correct value as shown. cont?o? registe? o?e?ating mode bit7 bit6 se?ect bits fo? the pu?se width ca?tu?e mode 1 1 in this mode the internal clock, f sys , is used as the internal clock for the 8-bit timer/event counter. however, the clock source, f sys , for the 8-bit timer is further divided by a prescaler, the value of which is determined by the prescaler rate select bits tpsc2~tpsc0, which are bits 2~0 in the timer control register. after the other bits in the timer control register have been setup, the enable bit ton, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit teg, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width capture mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the tmr pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. the timer cannot begin further pulse width capture until the enable bit is set high again by the program. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. when the timer/event counter is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register is reset to zero. as the tmr pin is shared with an i/o pin, to ensure that the pin is confgured to operate as a pulse width capture pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width capture mode, the second is to ensure that the port control register confgures the pin as an input.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 86 ???i? 01? ? 011 rev. 1.00 87 ???i? 01? ? 011

? ? ? ? ? ?? ? ? pulse width capture mode timing chart (te=0) prescaler bi ts tpsc0~tpsc2 of the tmrc register c an be used to define a division ratio for the internal clock source of the timer/event counter enabling longer time out periods to be setup. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width capture mode, requires the use of an external timer pin for its operation. as this pin is a shared pin it must be confgured correctly to ensure that it is setup for use as a timer/event counter input pin. this is achieved by ensuring that the mode select bits in the timer/event counter control register select either the event counter or pulse width capture mode. additionally the corresponding port control register bit must be set high to ensure that the pin is setup as an input. any pull-high resistor connected to this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width capture mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is confgured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly initialized before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is frst loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialized the timer can be turned on and off by controlling the enable bit in the timer control register.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 88 ???i? 01? ? 011 rev. 1.00 89 ???i? 01? ? 011 when the timer/event counter overfows, its corresponding interrupt request fag in the interrupt control register will be set. if the timer/event counter interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are enabled or not, a timer/event counter overfow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overfow occurs the device will be woken up from its power- down condition. to prevent such a wake-up from occurring, the timer interrupt request fag should frst be set high before issuing the halt instruction to enter the idle/sleep mode. timer/event counter program example the program shows how the timer/event counter registers are setup along with how the interrupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counters to be in the timer mode, which uses the internal system clock as their clock source. timer/event counter program example org 04h ; external interrupt vector org 30h ; timer/event counter interrupt vector jmp tmrint ; jump here when tmr overfows : : org 20h ; main program : : ;internal tmr interrupt routine tmrint: : ; tmr main program placed here : : begin: ;setup tmr registers mov a,09bh ; setup tmr preload value mov tmr,a mov a,080h ; setup tmr control register mov tmrc,a ; timer mode and prescaler set to /2 ;setup interrupt register mov a,00dh ; enable master interrupt and both timer interrupts mov intc0,a : : set tmrc.4 ; start tmr :
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 88 ???i? 01? ? 011 rev. 1.00 89 ???i? 01? ? 011 analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must frst be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contains a 8 channels analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. input channels a/d channel select bits input pins 8 ?cs4? ?cs?~?cs0 ?n0~?n7 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. a/d converter register description overall operation of the a/d converter is controlled using fve registers. a read only register pair exists to store the adc data 12-bit value. the remaining three registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 ?drl(?drfs=0) d3 d? d1 d0 ?drl(?drfs=1) d7 d6 d5 d4 d3 d? d1 d0 ?drh(?drfs=0) d11 d10 d9 d8 d7 d6 d5 d4 ?drh(?drfs=1) d11 d10 d9 d8 ?dcr0 st ? rt eocb ?doff ?drfs ?cs? ?cs1 ?cs0 ?dcr1 ?cs4 v1?5en vrefs ?dck? ?dck1 ?dck0 ?cer ?ce7 ?ce6 ?ce5 ?ce4 ?ce3 ?ce? ?ce1 ?ce0 a/d converter register list
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 90 ???i? 01? ? 011 rev. 1.00 91 ???i? 01? ? 011

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? ?? ? ? - ? - ? ? ? ? ? ? a/d converter structure a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter, they require two data registers to store the converted value. these are a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acer to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 and acer are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/ d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs2~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register define the adc input channel number. as the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter. it is the function of the acs4~acs0 bits to determine which analog channel input pins or internal 1.25v is actually connected to the internal a/d converter. the acer control register contains the acer7~acer0 bits which determine which pins on port a are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 90 ???i? 01? ? 011 rev. 1.00 91 ???i? 01? ? 011 adcr0 register bit 7 6 5 4 3 2 1 0 name st ? rt eocb ?doff ?drfs ?cs? ?cs1 ?cs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 bit 7 sr : start the a/d conversion 010: start 01 : reset the a/d converter and set eocb to "1" this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5 doff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 drfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 unimplemented, read as "0" bit 2~0 cs2 cs1 cs0 : select a/d channel (when acs4 is "0") 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 9? ???i? 01? ? 011 rev. 1.00 93 ???i? 01? ? 011 adcr1 register bit 7 6 5 4 3 2 1 0 name ?cs4 v1?5en vrefs ?dck? ?dck1 ?dck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 cs4 : selecte internal 1.25v as adc input control 0: disable 1: enable this bit enables 1.25v to be connected to the a/d converter. the v125en bit must frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v125e : internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/off function to the a/d converter. when the bit is set high the bandgap voltage 1.25v can be used by the a/d converter. if 1.25v is not used by the a/d converter and the lvr/lvd function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. when 1.25v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as "0" bit 4 vrefs : selecte adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter. if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as "0" bit 2~0 dc2 dc1 dc0 : select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 9? ???i? 01? ? 011 rev. 1.00 93 ???i? 01? ? 011 acer register bit 7 6 5 4 3 2 1 0 name ?ce7 ?ce6 ?ce5 ?ce4 ?ce3 ?ce? ?ce1 ?ce0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ce7 : defne pa7 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ce6 : defne pa6 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ce5 : defne pa5 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ce4 : defne pa4 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ce3 : defne pa3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ce2 : defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ce1 : defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ce0 : defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d operation the start bit in the adcr0 register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr0 register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 94 ???i? 01? ? 011 rev. 1.00 95 ???i? 01? ? 011 although the a/d clock source is determined by the system clocky,f sys , and by bits adck2~adck0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, tad, is 0.5s, care must be taken for system clock frequencies equal to or greater than 4mhz. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000. doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t ad ) adck2, adck1, adck0 = 000 (f sys ) adck2, adck1, adck0 = 001 (f sys /2) adck2, adck1, adck0 = 010 (f sys /4) adck2, adck1, adck0 = 011 (f sys /8) adck2, adck1, adck0 = 100 (f sys /16) adck2, adck1, adck0 = 101 (f sys /32) adck2, adck1, adck0 = 110 (f sys /64) adck2, adck1, adck0 = 111 1mhz 1us ? us 4 us 8 us 16 us 3? us 64 us undefned ?mhz 500ns 1 us ? us 4 us 8 us 16 us 3? us undefned 4mhz ?50ns* 500ns 1 us ? us 4 us 8 us 16 us undefned 8mhz 1?5ns* ?50ns* 500ns 1 us ? us 4 us 8 us undefned 1?mhz 83ns* 167ns* 333ns* 667ns 1.33 us ?.67 us 5.33 us undefned a/d clock period examples controlling the power on/off function of the a/d converter circuitry is implemented using the adoff bit in the adcr0 register. this bit must be zero to power on the a/d converter. even if no pins are selected for use as a/d inputs by clearing the ace7~ace0 bits in the acer register, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref. the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a as well as other functions. the ace7~ ace0 bits in the acer register, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace7~ ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pac port control register to enable the a/d input as when the ace7~ ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of vref.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 94 ???i? 01? ? 011 rev. 1.00 95 ???i? 01? ? 011
? ? ? ? ?? ? ? - a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr1 and adcr0 register. step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace7~ace0 bits in the acer register. step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bit, eadi, must both be set high to do this. step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr register from low to high and then low again. note that this bit should have been originally cleared to zero. step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t ad where t ad is equal to the a/d clock period.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 96 ???i? 01? ? 011 rev. 1.00 97 ???i? 01? ? 011

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? ? ? - ? ? ? ? ?? - a/d conversion timing programming considerations during microcontroller operations where the a/d converter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by setting bit adoff high in the adcr0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. ref the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = ref the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 96 ???i? 01? ? 011 rev. 1.00 97 ???i? 01? ? 011 a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr eadi ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acer to confgure pins an0~an3 mov acer,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : jmp start_conversion ; start next a/d conversion
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 98 ???i? 01? ? 011 rev. 1.00 99 ???i? 01? ? 011 example: using the interrupt method to detect the end of conversion clr eadi ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acer to confgure pins an0~an3 mov acer,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set eadi ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 98 ???i? 01? ? 011 rev. 1.00 99 ???i? 01? ? 011 comparator a s ingle independent analog comparator is contained within this device. this function offers flexibility via its register controlled features such as power-down, polarity select, hysteresis etc. in sharing its pins with normal i/o pins the comparator do es not waste precious i/o pins if there functions are otherwise unused. comparator comparator operation the device contains a single comparator which is used to compare two analog voltages and provide an output based on their difference. full control over the one internal comparator is provided via the control register, cpc. the comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a shared i/o pin. additional comparator functions include, output polarity, hysteresis functions and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. comparator registers there is one register for overall comparator operation. cpc register bit 7 6 5 4 3 2 1 0 name csel cen cpol cout cos chyen r/w r/w r/w r/w r r/w r/w por 1 0 0 0 0 1 bit 7 cse : select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 ce : comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 100 ???i? 01? ? 011 rev. 1.00 101 ???i? 01? ? 011 not used or before the device enters the sleep or idle mode. bit 5 cpol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the cout bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator cout bit will be inverted. bit 4 cout : comparator output bit cpol=0 0: c+ < c- 1: c+ > c- cpol=1 0: c+ > c- 1: c+ < c- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the cpol bit. bit 3 cos : output path select 0: cx pin 1: internal use this is the comparator output path select control bit. if the bit is set to 0and the csel bit is 1 the comparator output is connected to an external cx pin. if the bit is set to 1 or the csel bit is 0 the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as 0 bit 0 chyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. the comparator also possesses an interrupt function. when the comparator changes state, its relevant interrupt fag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the c0out bit and not the output pin which generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt fag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode. if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control register is 1) or read as port data register value (port control register is 0) if the comparator function is enabled.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 100 ???i? 01? ? 011 rev. 1.00 101 ???i? 01? ? 011 serial interface module C sim this device contains two serial interface modules, sim0 and sim1, which include both the four line spi interface and the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. note that the sim1 interface function must first be selected using a configuration option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the simn operating mode control bits, named snsim2~snsim0, in the simnc0 register. the index n, shown as 0 or 1, is used to distinguish these two sim modules. these pull-high resistors of the sim1 pin-shared i/o are selected using pull-high control registers, and also if the sim1 function is enabled. spin interface the spin interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spin interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spin interface specifcation can control multiple slave devices from a single master, but this device provided only one scsn pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spin interface operation the spin interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdin, sdon, sckn and scsn. pins sdin and sdon are the serial data input and serial data output lines, sckn is the serial clock line and scsn is the slave select line. as the spi1 interface pins are pin-shared with normal i/o pins and with the i 2 c1 function pins, the spi1 interface must frst be enabled by selecting the sim1 enable confguration option and setting the correct bits in the sim1c0 and sim1c2 registers. after the spi1 confguration option has been confgured it can also be additionally disabled or enabled using the s1simen bit in the sim1c0 register. about the spi0, the interface pins are pin-shared with the i 2 c0 function pins, therefore, the spi0 interface must be enabled by setting the correct bits in the sim0c0 and sim0c2 registers.communication between devices connected to the spin interface is carried out in a slave/ master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scsn pin only one slave device can be utilized. the scsn pin is controlled by software, set sncsen bit to 1 to enable scsn pin function, set sncsen bit to 0 the scsn pin will be foating state. spi master/slave connection
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 10? ???i? 01? ? 011 rev. 1.00 103 ???i? 01? ? 011 the spin function in this device offers the following features: full duplex synchronous data transfer both master and slave modes lsb frst or msb frst data transmission modes transmission complete fag rising or falling active clock edge snwcol and sncsen bit enabled or disable select the status of the spin interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as sncsen and snsimen. there are several configuration options associated with the spin interface. one of these is to enable the sim1 function which selects the sim1 pins rather than normal i/o pins. note that if the confguration option does not select the sim1 function then the s1simen bit in the sim1c0 register will have no effect. another two spin confguration options determine if the sncsen and snwcol bits are to be used. spin registers there are several internal registers which control the overall operation of the spin interface. these are the simnd data register and two registers simnc0 and simnc2. note that the simnc1 register is only used by the i 2 cn interface. register name bit 7 6 5 4 3 2 1 0 sim0c0 s0sim? s0sim1 s0sim0 s0simen sim1c0 s1sim? s1sim1 s1sim0 s1pcken s1pckp1 s1pckp0 s1simen simnd snd7 snd6 snd5 snd4 snd3 snd? snd1 snd0 simnc? snd7 snd6 snckpolb snckeg snmls sncsen snwcol sntrf note: n="0" o? "1"

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HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 10? ???i? 01? ? 011 rev. 1.00 103 ???i? 01? ? 011 simn registers list the simnd register is used to store the data being transmitted and received. the same register is used by both the spin and i 2 cn functions. before the device writes data to the spin bus, the actual data to be transmitted must be placed in the simnd register. after the data is received from the spin bus, the device can read it from the simnd register. any transmission or reception of data from the spin bus must be made via the simnd register. simnd register bit 7 6 5 4 3 2 1 0 name snd7 snd6 snd5 snd4 snd3 snd? snd1 snd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x ? "x" unknown there are also two control registers for the spin interface, simnc0 and simnc2. note that the simnc2 register also has the name simna which is used by the i 2 cn function. the simnc1 register is not used by the spin function, only by the i 2 cn function. register simnc0 is used to control the enable/disable function and to set the data transmission clock frequency. although not connected with the spi function, the sim1c0 register is also used to control the peripheral clock prescaler. register simnc2 is used for other control functions such as lsb/msb selection, write collision fag etc. sim0c0 register bit 7 6 5 4 3 2 1 0 name s0sim? s0sim1 s0sim0 s0simen r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 s0sim2 s0sim1 s0sim0 : sim0 operating mode control 000: spi0 master mode; spi0 clock is f sys /4 001: spi0 master mode; spi0 clock is f sys /16 010: spi0 master mode; spi0 clock is f sys /64 011: spi0 master mode; spi0 clock is f tbc 100: spi0 master mode; spi0 clock is tm0 ccrp match frequency/2 101: spi0 slave mode 110: i 2 c0 slave mode 111: unused mode these bits setup the overall operating mode of the sim0 function. as well as selecting if the i 2 c0 or spi0 function, they are used to control the spi0 master/slave selection and the spi0 master clock frequency. the spi0 clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi0 slave mode is selected then the clock will be supplied by an external master device. bit 4~2 unimplemented, read as 0 bit 1 s0sime : sim0 control 0: disable 1: enable the bit is the overall on/off control for the sim0 interface. when the s0simen bit is cleared to zero to disable the sim0 interface, the sdi0, sdo0, sck0 and scs0, or sda0 and scl0 lines will be in a floating condition and the sim0 operating current will be reduced to a minimum value. when the bit is high the sim0 interface is enabled. the sim0 confguration option must have frst enabled the sim0 interface for this bit to be effective. if the sim0 is confgured to operate as an spi0 interface via the s0sim2~s0sim0 bits, the contents of the spi0 control registers will remain at the previous settings when the s0simen bit changes from low to high and should
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 104 ???i? 01? ? 011 rev. 1.00 105 ???i? 01? ? 011 therefore be first initialised by the application program. if the sim0 is configured to operate as an i 2 c0 interface via the s0sim2~s0sim0 bits and the s0simen bit changes from low to high, the contents of the i 2 c0 control bits such as s0htx and s0txak will remain at the previous settings and should therefore be frst initialised by the application program while the relevant i 2 c0 fags such as s0hcf, s0haas, s0hbb, s0srw and s0rxak will be set to their default states. bit 0 unimplemented, read as 0 sim1c0 register bit 7 6 5 4 3 2 1 0 name s1sim? s1sim1 s1sim0 pcken pckp1 pckp0 s1simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 0 bit 7~5 s1sim2 s1sim1 s1sim0 : sim1 operating mode control 000: spi1 master mode; spi1 clock is f sys /4 001: spi1 master mode; spi1 clock is f sys /16 010: spi1 master mode; spi1 clock is f sys /64 011: spi1 master mode; spi1 clock is f tbc 100: spi1 master mode; spi1 clock is tm0 ccrp match frequency/2 101: spi1 slave mode 110: i 2 c1 slave mode 111: unused mode these bits setup the overall operating mode of the sim1 function. as well as selecting if the i 2 c1 or spi1 function, they are used to control the spi1 master/slave selection and the spi1 master clock frequency. the spi1 clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi1 slave mode is selected then the clock will be supplied by an external master device. bit 4 pce : pck output pin control 0: disable 1: enable bit 3~2 pcp1 pcp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 s1sime : sim1 control 0: disable 1: enable the bit is the overall on/off control for the sim1 interface. when the s1simen bit is cleared to zero to disable the sim1 interface, the sdi1, sdo1, sck1 and scs1, or sda1 and scl1 lines will be in a floating condition and the sim1 operating current will be reduced to a minimum value. when the bit is high the sim1 interface is enabled. the sim1 confguration option must have frst enabled the sim1 interface for this bit to be effective. if the sim1 is confgured to operate as an spi1 interface via the s1sim2~s1sim0 bits, the contents of the spi1 control registers will remain at the previous settings when the s1simen bit changes from low to high and should therefore be first initialised by the application program. if the sim1 is configured to operate as an i 2 c1 interface via the s1sim2~s1sim0 bits and the s1simen bit changes from low to high, the contents of the i 2 c1 control bits such as s1htx and s1txak will remain at the previous settings and should therefore be frst initialised by the application program while the relevant i 2 c1 fags such as s1hcf, s1haas, s1hbb, s1srw and s1rxak will be set to their default states. bit 0 unimplemented, read as 0
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 104 ???i? 01? ? 011 rev. 1.00 105 ???i? 01? ? 011 simnc2 register bit 7 6 5 4 3 2 1 0 name snd7 snd6 snckpolb snckeg snmls sncsen snwcol sntrf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bit this bit can be read or written by user software program. bit 5 sncpob : determines the base condition of the clock line 0: the sckn line will be high when the clock is inactive 1: the sckn line will be low when the clock is inactive the snckpolb bit determines the base condition of the clock line, if the bit is high, then the sckn line will be low when the clock is inactive. when the snckpolb bit is low, then the sckn line will be high when the clock is inactive. bit 4 snce : determines spin sckn active clock edge type snckpolb=0 0: sckn is high base level and data capture at sckn rising edge 1: sckn is high base level and data capture at sckn falling edge snckpolb=1 0: sckn is low base level and data capture at sckn falling edge 1: sckn is low base level and data capture at sckn rising edge the snckeg and snckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spin bus. these two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. the snckpolb bit determines the base condition of the clock line, if the bit is high, then the sckn line will be low when the clock is inactive. when the snckpolb bit is low, then the sckn line will be high when the clock is inactive. the snckeg bit determines active clock edge type which depends upon the condition of snckpolb bit. bit 3 snms : spin data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 sncse : spin scsn pin control 0: disable 1: enable the sncsen bit is used as an enable/disable for the scsn pin. if this bit is low, then the scsn pin will be disabled and placed into a foating condition. if the bit is high the scsn pin will be enabled and used as a select pin. note that using the sncsen bit can be disabled or enabled via confguration option. bit 1 snco : spin write collision fag 0: no collision 1: collision the snwcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simnd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the snwcol bit can be disabled or enabled via confguration option. bit 0 snrf : spin transmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the sntrf bit is the transmit/receive complete flag and is set 1automatically when an spin data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 106 ???i? 01? ? 011 rev. 1.00 107 ???i? 01? ? 011 spi communication after the spin interface is enabled by setting the snsimen bit high, then in the master mode, when data is written to the simnd register, transmission/reception will begin simultaneously. when the data transfer is complete, the sntrf fag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simnd register will be transmitted and any data on the sdin pin will be shifted into the simnd register. the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the snckpolb bit and snckeg bit. the accompanying timing diagram shows the relationship between the slave data and snscs signal for various confgurations of the snckpolb and snckeg bits. the spin will continue to function even in the idle mode.
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HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 106 ???i? 01? ? 011 rev. 1.00 107 ???i? 01? ? 011

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? ? ? ? ? ? - ? ?? ? ? ?? ? ? ?? ?? ? ?? ? ??? ??? ? ?? ? ?? ?? ? spin transfer control flowchart i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 108 ???i? 01? ? 011 rev. 1.00 109 ???i? 01? ? 011 i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several confguration options associated with the i 2 cn interface. one of these is to enable the function which selects the sim1 pins rather than normal i/o pins. note that if the confguration option does not select the sim1 function then the s1simen bit in the sim1c0 register will have no effect. a confguration option exists to allow a clock other than the system clock to drive the i 2 cn interface. another configuration option determines the debounce time of the i 2 cn interface. this uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks.
i 2 cn registers there are several control registers associated with the i 2 cn bus, simnc0, simnc1 and simna and data register, simnd. the simnd register, which is shown in the above spin section, is used to store the data being transmitted and received on the i 2 cn bus. before the microcontroller writes data to the i 2 cn bus, the actual data to be transmitted must be placed in the simnd register. after the data is received from the i 2 cn bus, the microcontroller can read it from the simnd register. any transmission or reception of data from the i 2 cn bus must be made via the simnd register. note that the simna register also has the name simnc2 which is used by the spin function. bit snsimen and bits snsim2~snsim0 in register simnc0 are used by the i 2 c interface.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 108 ???i? 01? ? 011 rev. 1.00 109 ???i? 01? ? 011 register name bit 7 6 5 4 3 2 1 0 sim0c0 s0sim? s0sim1 s0sim0 s0simen sim1c0 snsim? snsim1 snsim0 pcken pckp1 pckp0 simen simnc1 snhcf snh?ns snhbb snhtx sntx?k snsrw sni?mwu snrx?k simnd snd7 snd6 snd5 snd4 snd3 snd? snd1 snd0 simn? sniic?6 sniic?5 sniic?4 sniic?3 sniic?? sniic?1 sniic?0 note: n=0 o? 1 i 2 c registers list sim0c0 register bit 7 6 5 4 3 2 1 0 name s0sim? s0sim1 s0sim0 s0simen r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 s0sim2 s0sim1 s0sim0 : sim0 operating mode control 000: spi0 master mode; spi0 clock is f sys /4 001: spi0 master mode; spi0 clock is f sys /16 010: spi0 master mode; spi0 clock is f sys /64 011: spi0 master mode; spi0 clock is f tbc 100: spi0 master mode; spi0 clock is tm0 ccrp match frequency/2 101: spi0 slave mode 110: i 2 c0 slave mode 111: unused mode these bits setup the overall operating mode of the sim0 function. as well as selecting if the i 2 c0 or spi0 function, they are used to control the spi0 master/slave selection and the spi0 master clock frequency. the spi0 clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi0 slave mode is selected then the clock will be supplied by an external master device. bit 4~2 unimplemented, read as 0 bit 1 s0sime : sim0 control 0: disable 1: enable the bit is the overall on/off control for the sim0 interface. when the s0simen bit is cleared to zero to disable the sim0 interface, the sdi0, sdo0, sck0 and scs0, or sda0 and scl0 lines will be in a floating condition and the sim0 operating current will be reduced to a minimum value. when the bit is high the sim0 interface is enabled. the sim0 confguration option must have frst enabled the sim0 interface for this bit to be effective. if the sim0 is confgured to operate as an spi0 interface via the s0sim2~s0sim0 bits, the contents of the spi0 control registers will remain at the previous settings when the s0simen bit changes from low to high and should therefore be first initialised by the application program. if the sim0 is configured to operate as an i 2 c0 interface via the s0sim2~s0sim0 bits and the s0simen bit changes from low to high, the contents of the i 2 c0 control bits such as s0htx and s0txak will remain at the previous settings and should therefore be frst initialised by the application program while the relevant i 2 c0 fags such as s0hcf, s0haas, s0hbb, s0srw and s0rxak will be set to their default states. bit 0 unimplemented, read as 0
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 110 ???i? 01? ? 011 rev. 1.00 111 ???i? 01? ? 011 sim1c0 register bit 7 6 5 4 3 2 1 0 name s1sim? s1sim1 s1sim0 pcken pckp1 pckp0 s1simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 0 bit 7~5 s1sim2 s1sim1 s1sim0 : sim1 operating mode control 000: spi1 master mode; spi1 clock is f sys /4 001: spi1 master mode; spi1 clock is f sys /16 010: spi1 master mode; spi1 clock is f sys /64 011: spi1 master mode; spi1 clock is f tbc 100: spi1 master mode; spi1 clock is tm0 ccrp match frequency/2 101: spi1 slave mode 110: i 2 c1 slave mode 111: unused mode these bits setup the overall operating mode of the sim1 function. as well as selecting if the i 2 c1 or spi1 function, they are used to control the spi1 master/sl ave selection and the spi1 master clock frequency. the spi1 clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi1 slave mode is selected then the clock will be supplied by an external master device. bit 4 pce : pck output pin control 0: disable 1: enable bit 3~2 pcp1 pcp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 s1sime : sim1 control 0: disable 1: enable the bit is the overall on/off control for the sim1 interface. when the s1simen bit is cleared to zero to disable the sim interface, the sdi1, sdo1, sck1 and scs1, or sda1 and scl1 lines will be in a foating condition and the sim1 operating current will be reduced to a minimum value. when the bit is high the sim1 interface is enabled. the sim1 confguration option must have frst enabled the sim1 interface for this bit to be effective. if the sim1 is confgured to operate as an spi1 interface via the s1sim2~s1sim0 bits, the contents of the spi1 control registers will remain at the previous settings when the s1simen bit changes from low to high and should therefore be first initialised by the application program. if the sim1 is configured to operate as an i 2 c1 interface via the s1sim2~s1sim0 bits and the s1simen bit changes from low to high, the contents of the i 2 c1 control bits such as s1htx and s1txak will remain at the previous settings and should therefore be frst initialised by the application program while the relevant i 2 c1 fags such as s1hcf, s1haas, s1hbb, s1srw and s1rxak will be set to their default states. bit 0 unimplemented, read as 0
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 110 ???i? 01? ? 011 rev. 1.00 111 ???i? 01? ? 011 simnc1 register bit 7 6 5 4 3 2 1 0 name snhcf snh?ns snhbb snhtx sntx?k snsrw sni?mwu snrx?k r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 snhcf : i 2 cn bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the snhcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 snhs : i 2 cn bus address match fag 0: not address match 1: address match the snhass fag is the address match fag. this fag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low . bit 5 snhbb : i 2 cn bus busy fag 0: i 2 cn bus is not busy 1: i 2 cn bus is busy the snhbb fag is the i 2 cn busy fag. this fag will be 1 when the i 2 cn bus is busy which will occur when a start signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 snh : select i 2 cn slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 sn : i 2 cn bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the sntxak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set sntxak bit to 0 before further data is received. bit 2 snsr : i 2 cn slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the snsrw flag is the i 2 cn slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i 2 cn bus. when the transmitted address and slave address is match, that is when the snhaas fag is set high, the slave device will check the snsrw fag to determine whether it should be in transmit mode or receive mode. if the snsrw fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the snsrw fag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 snimu : i 2 cn address match wake-up control 0: disable 1: enable this bit should be set to 1 to enable i 2 cn address match wake up from sleep or idle mode. bit 0 snr : i 2 cn bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 11 ? ???i? 01? ? 011 rev. 1.00 113 ???i? 01? ? 011 the snrxak fag is the receiver acknowledge fag. when the snrxak fag is 0, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the snrxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the snrxak fag is 1. when this occurs, the slave transmitter will release the sdan line to allow the master to send a stop signal to release the i 2 cn bus. the simnd register is used to store the data being transmitted and received. the same register is used by both the spin and i 2 cn functions. before the device writes data to the spin bus, the actual data to be transmitted must be placed in the simnd register. after the data is received from the spin bus, the device can read it from the simnd register. any transmission or reception of data from the spin bus must be made via the simnd register. simnd register bit 7 6 5 4 3 2 1 0 name snd7 snd6 snd5 snd4 snd3 snd? snd1 snd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x ? "x" unknown simna register bit 7 6 5 4 3 2 1 0 name sniic?6 sniic?5 sniic?4 sniic?3 sniic?? sniic?1 sniic?0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x 0 ? "x" unknown bit 7~1 iic6~ iic0 : i 2 cn slave address sniica6~ sniica0 is the i 2 cn slave address bit 6~ bit 0. the simna register is also used by the spin interface but has the name simnc2. the simna register is the location where the 7-bit slave address of the slave device is stored. bits 7~ 1 of the simna register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 cn bus, sends out an address, which matches the slave address in the simna register, the slave device will be selected. note that the simna register is the same register address as simnc2 which is used by the spin interface. bit 0 undefned bit this bit can be read or written by user software program.

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HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 11 ? ???i? 01? ? 011 rev. 1.00 113 ???i? 01? ? 011 i 2 cn bus communication communication on the i 2 cn bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and fnally a stop signal. when a start signal is placed on the i 2 cn bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the snhaas bit in the simnc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must first check the condition of the snhaas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the snsrw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 set the snsim2~snsim0 and snsimen bits in the simnc0 register to 1 to enable the i 2 c bus. step 2 write the slave address of the device to the i 2 c bus address register simna. step 3 set the simne and sim muti-function interrupt enable bit of the interrupt control register to enable the simn interrupt and multi-function interrupt.
? ? ? ? ? ? - ? ? ? ? ? ?? ? ? ? ? ? - i 2 cn bus initialisation flow chart
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 114 ???i? 01? ? 011 rev. 1.00 115 ???i? 01? ? 011 i 2 cn bus start signal the start signal can only be generated by the master device connected to the i 2 cn bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 cn bus. when detected, this indicates that the i 2 cn bus is busy and therefore the snhbb bit will be set. a start condition occurs when a high to low transition on the sdan line takes place when the scln line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 cn bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 cn bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the snsrw bit of the simnc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag snhaas when the addresses match. as an i 2 cn bus interrupt can come from two sources, when the program enters the interrupt subroutine, the snhaas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simnd register, or in the receive mode where it must implement a dummy read from the simnd register to release the scln line. i 2 cn bus read/write signal the snsrw bit in the simnc1 register defnes whether the slave device wishes to read data from the i 2 cn bus or write data to the i 2 cn bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the snsrw fag is 1 then this indicates that the master device wishes to read data from the i 2 cn bus, therefore the slave device must be setup to send data to the i 2 cn bus as a transmitter. if the snsrw fag is 0 then this indicates that the master wishes to send data to the i 2 cn bus, therefore the slave device must be setup to read data from the i 2 cn bus as a receiver. i 2 cn bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 cn bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas flag is high, the addresses have matched and the slave device must check the snsrw fag to determine if it is to be a transmitter or a receiver. if the snsrw fag is high, the slave device should be setup to be a transmitter so the snhtx bit in the simnc1 register should be set to 1. if the snsrw fag is low, then the microcontroller slave device should be setup as a receiver and the snhtx bit in the simnc1 register should be set to 0.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 114 ???i? 01? ? 011 rev. 1.00 115 ???i? 01? ? 011 i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0, before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sdan line to allow the master to send a stop signal to release the i 2 cn bus. the corresponding data will be stored in the simnd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simnd register. if setup as a receiver, the slave device must read the transmitted data from the simnd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as sntxak, on the 9th clock. the slave device, which is setup as a transmitter will check the snrxak bit in the simnc1 register to determine if it is to send another data byte, if not then it will release the sdan line and await the receipt of a stop signal from the master.

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note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simnd register, or in the receive mode where it must implement a dummy read from the simnd register to release the scln line. i 2 cn communication timing diagram
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 116 ???i? 01? ? 011 rev. 1.00 117 ???i? 01? ? 011
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i 2 cn bus isr flow chart
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 116 ???i? 01? ? 011 rev. 1.00 117 ???i? 01? ? 011 peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the sim1c0 register. the peripheral clock function is controlled using the sim1c0 register. the clock source for the peripheral clock output can originate from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the sim1c0 register is the overall on/off control, setting pcken bit to 1 enables the peripheral clock, setting pcken bit to 0 disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock output. sim1c0 register bit 7 6 5 4 3 2 1 0 name s1sim? s1sim1 s1sim0 pcken pckp1 pckp0 s1simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 s1sim2s1sim1 s1sim0 : sim1 operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim1 function. as well as selecting if the i 2 c1 or spi1 function, they are used to control the spi1 master/slave selection and the spi1 master clock frequency. the spi1 clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi1 slave mode is selected then the clock will be supplied by an external master device. bit 4 pce : pck output pin control 0: disable 1: enable bit 3~2 pcp1 pcp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 s1sime : sim1 control 0: disable 1: enable the bit is the overall on/off control for the sim1 interface. when the s1simen bit is cleared to zero to disable the sim1 interface, the sdi1, sdo1, sck1 and scs1, or sda1 and scl1 lines will be in a floating condition and the sim1 operating current will be reduced to a minimum value. when the bit is high the sim1 interface is enabled. the sim1 confguration option must have frst enabled the sim1 interface for this bit to be effective. note that when the s1simen bit changes from low to high the contents of the spi1 control registers will be in an unknown condition and should therefore be frst initialised by the application program. bit 0 unimplemented, read as 0
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 118 ???i? 01? ? 011 rev. 1.00 119 ???i? 01? ? 011 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int1 and pint pins, while the internal interrupts are generated by various internal functions such as the tms, timer, comparator, time base, lvd, sims and the a/d converter. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi3 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes g?oba? emi com?a?ato? cpe cpf intn pin intne intnf n = 0 o? 1 ?/d conve?te? ?de ?df mu?ti-function mfne mfnf n = 0~? time base tbne tbnf n = 0 o? 1 sim simne simnf n = 0 o? 1 lvd lve lvf pint pin xpe xpf tmn0 tnpe tnpf n = 0 tn?e tn?f tmn1 tnpe tnpf n = 1 tn?e tn?f tnbe tnbf interrupt register bit naming conventions interrupt register contents name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cpf int1f int0f cpe int1e int0e emi intc1 ?df mf1f mf0f sim0f ?de mf1e mf0e sim0e intc? lvf tb1f tb0f mf?f lve tb1e tb0e mf?e intc3 tf te mfi0 t0?f t0pf t0?e t0pe mfi1 t1bf t1?f t1pf t1be t1?e t1pe mfi? xpf sim1f xpe sim1e
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 118 ???i? 01? ? 011 rev. 1.00 119 ???i? 01? ? 011 integ register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~2 i1s1 i1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 i0s1 i0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges intc0 register bit 7 6 5 4 3 2 1 0 name cpf int1f int0f cpe int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 cpf : comparator interrupt request fag 0: no request 1: interrupt request bit 5 i1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 i0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 cpe : comparator interrupt control 0: disable 1: enable bit 2 i1e : int1 interrupt control 0: disable 1: enable bit 1 i0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?0 ???i? 01? ? 011 rev. 1.00 1?1 ???i? 01? ? 011 intc1 register bit 7 6 5 4 3 2 1 0 name ?df mf1f mf0f sim0f ?de mf1e mf0e sim0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 df : a/d converter interrupt request flag 0: no request 1: interrupt request bit 6 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 5 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 4 sim0f : sim 0 interrupt request flag 0: no request 1: interrupt request bit 3 de : a/d converter interrupt control 0: disable 1: enable bit 2 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 1 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 0 sim0e : sim 0 interrupt control 0: disable 1: enable intc2 register bit 7 6 5 4 3 2 1 0 name lvf tb1f tb0f mf?f lve tb1e tb0e mf?e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 vf : lvd interrupt request flag 0: no request 1: interrupt request bit 6 b1f : time base 1 interrupt request flag 0: no request 1: interrupt request bit 5 b0f : time base 0 iinterrupt request flag 0: no request 1: interrupt request bit 4 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 3 ve : lvd interrupt control 0: disable 1: enable
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?0 ???i? 01? ? 011 rev. 1.00 1?1 ???i? 01? ? 011 bit 2 tb1e : time base 1 interrupt control 0: disable 1: enable bit 1 tb0e : time base 0 interrupt control 0: disable 1: enable bit 0 mf2e : multi-function interrupt 2 control 0: disable 1: enable name tf te r/w r/w r/w por 0 0 bit 7~5 unimplemented, read as "0" bit 4 tf : tmr interrupt request fag 0: no request 1: interrupt request bit 3~1 unimplemented, read as 0 bit 0 te : tmr interrupt control 0: disable 1: enable name t0?f t0pf t0?e t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?? ???i? 01? ? 011 rev. 1.00 1?3 ???i? 01? ? 011 mfi1 register bit 7 6 5 4 3 2 1 0 name t1bf t1?f t1pf t1be t1?e t1pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 1bf : tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 1f : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 1pf : tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 1be : tm1 comparator p match interrupt control 0: disable 1: enable bit 1 1e : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 1pe : tm1 comparator p match interrupt control 0: disable 1: enable mfi2 register bit 7 6 5 4 3 2 1 0 name xpf sim1f xpe sim1e r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 pf : external peripheral interrupt request fag 0: no request 1: interrupt request bit 4 sim1f : sim1 interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 pe : external peripheral interrupt control 0: disable 1: enable bit 0 sim1e : sim1 interrupt control 0: disable 1: enable
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?? ???i? 01? ? 011 rev. 1.00 1?3 ???i? 01? ? 011 interrupt operation when the conditions for an interrupt event occur, such as a tm compar e p, compar e a or compar e b match or a/d conversion completion etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request fags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?4 ???i? 01? ? 011 rev. 1.00 1?5 ???i? 01? ? 011 04h 14h 18h 1ch ?0h ?4h ?8h vector low p ? io ? ity high request f ? ags enab ? e bits maste ? enab ? e request f ? ags enab ? e bits emi auto disab ? ed in isr inte ?? u? ts contained within mu? ti - function inte ?? u? ts inte ?? u?t name inte ?? u?t name xpf pint pin xpe ? ch emi emi emi emi emi emi sim1f sim1 sim1e t1bf tm1 b t1be t1 ?f tm1 ? t1 ?e t1pf tm1 p t1pe t0 ?f tm0 ? t0 ?e t0pf tm0 p t0pe int0f int0 pin int0e 08h emi int1f int1 pin int1e 08h emi int1f int1 pin int1e mf0f m. funct . 0 mf0e mf1f m. funct . 1 mf1e ? df ? /d ? de emi mf ?f m. funct . ? mf ?e tb0f time base 0 tb0e tb1f time base 1 tb1e xxf legend request f ? ag C no auto ? eset in isr xxf request f ? ag C auto ? eset in isr xxe enab ? e bit 10h emi sim0f sim 0 sim0e 10h emi sim0f sim 0 sim0e lvf lvd lve emi tf tmr te emi 30h emi cpf com ?. cpe 0ch emi cpf com ?. cpe 0ch interrupt structure external interrupt the external interrupts are controlled by signal transitions on the pins int0 and int1. an external interrupt request will take place when the external interrupt request fags, int0f , int1f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e , int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, int0f , int1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?4 ???i? 01? ? 011 rev. 1.00 1?5 ???i? 01? ? 011 comparator interrupt the comparator interrupt is controlled by the one internal comparator. a comparator interrupt request will take place when the comparator interrupt request fag, cpf, is set, a situation that will occur when the comparator output changes state. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bit, cpe, must frst be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt within these devices there are up to three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, sim1 interrupt, external peripheral interrupt and lvd interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf2f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt fags will be automatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts, sim1 interrupt, external peripheral interrupt and lvd interrupt will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, te, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request fag, tf, is set, a situation that will occur when the relevant timer/event counter overfows. when the interrupt is enabled, the stack is not full and a timer/event counter overfow occurs, a subroutine call to the relevant timer interrupt vector, will take place. when the interrupt is serviced, the timer interrupt request fag, tf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?6 ???i? 01? ? 011 rev. 1.00 1?7 ???i? 01? ? 011 time base interrupts the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section. tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 tb0? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 bo : tb0 and tb1 control 0: disable 1: enable bit 6 bc : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 b11~b10 : select time base 1 time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 unimplemented, read as 0 bit 2~0 b02~b00 : select time base 0 time-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?6 ???i? 01? ? 011 rev. 1.00 1?7 ???i? 01? ? 011

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time base interrupt serial interface module interrupts there are two serial interface module interrupts, known as the sim0 and sim1 interrupts. the sim0 interrupt has its specifc interrupt vector address and the sim1 interrupt is contained within the multi-function interrupt. a simn interrupt request will take place when the simn interrupt request fag, simnf, is set, which occurs when a byte of data has been received or transmitted by the simn interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, simne, must first be set. note that, for sim1, the respective muti-function interrupt enable bits should also be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the simn interface, a subroutine call to the respective interrupt v ector or multi-function interrupt vector, will take place. when the serial interface interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the sim0f fag and the multi-function interrupt request fag will be also automatically cleared. as the sim1f fag will not be automatically cleared, it has to be cleared by the application program. external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt request fag, xpf, is set, which occurs when a negative edge transition appears on the pint pin. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, external peripheral interrupt enable bit, xpe, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a negative transition appears on the external peripheral interrupt pin, a subroutine call to the respective multi-function interrupt, will take place. when the external peripheral interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the xpf fag will not be automatically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with different functions. it must therefore be properly confgured to enable it to operate as an external peripheral interrupt pin.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?8 ???i? 01? ? 011 rev. 1.00 1?9 ???i? 01? ? 011 lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. an lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the lvf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact type tm has two interrupts, while the enhanced type tm has three interrupts. all of the tm interrupts are contained within the multi-function interrupts. for the compact type tm there is two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced type tm there are three interrupt request fags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 1?8 ???i? 01? ? 011 rev. 1.00 1?9 ???i? 01? ? 011 programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request fag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mf0f~mf2f, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 130 ???i? 01? ? 011 rev. 1.00 131 ???i? 01? ? 011 power down mode and wake-up entering the idle or sleep mode there is only one way for the device to enter the sleep or idle mode and that is to execute the "halt" instruction in the application program. when this instruction is executed, the following will occur: the system clock will be stopped and the application program will stop at the "halt" instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock source and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lirc oscillator . wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the "halt" instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 130 ???i? 01? ? 011 rev. 1.00 131 ???i? 01? ? 011 low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be detemined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 vdo : lvd output flag 0: no low voltage detect 1: low voltage detect bit vde : low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vvd2 ~ vvd0 : select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.4v
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 13? ???i? 01? ? 011 rev. 1.00 133 ???i? 01? ? 011 lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.4v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low voltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of tlvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. scom function for lcd the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~ scom3, are pin shared with certain pin on the pc0 ~ pc1, pc6 ~ pc7 port. the lcd signals (com and seg) are generated using the application program. lcd operation an external lcd panel can be driven using this device by confguring the pc0 ~ pc1, pc6 ~ pc7 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port c pins are used for lcd driving. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 13? ???i? 01? ? 011 rev. 1.00 133 ???i? 01? ? 011
lcd com bias comen comnen pin function o/p level 0 x i/o 0 o? 1 1 0 i/o 0 o? 1 1 1 scomn v dd /? output control lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. bit 7 6 5 4 3 2 1 0 name d7 isel1 isel0 scomen com3en com?en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 reserved bit 0: correct level - bit must be reset to zero for correct operation 1: unpredictable operation - bit must not be set high bit 6~5 ise1 ise0 : isel1 ~ isel0: select scom typical bias current (vdd=5v) 00: 25ma 01: 50ma 10: 100ma 11: 200ma bit 4 scome : scom module control 0: disable 1: enable bit 3 com3e : pc3 or scom3 selection 0: gpio 1: scom3 bit 2 com2e : pc2 or scom2 selection 0: gpio 1: scom2 bit 1 com1e : pc1 or scom1 selection 0: gpio 1: scom1 bit 0 com0e : pc0 or scom0 selection 0: gpio 1: scom0
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 134 ???i? 01? ? 011 rev. 1.00 135 ???i? 01? ? 011 digitial to analog converter C da c the voice control register controls the dac circuit. if the dac circuit is not enabled, any dah/dal outputs will be invalid. to write a 1 to the dacen bit will enable the dac circuit and output to corresponding i/o, while writing a 0 to the dacen bit will disable the dac circuit. audio output and volume control C dal, dah, vol, misc the audio output is 12-bits wide whose highest 8-bits are written into the dah register and whose lowest four bits are written into the highest four bits of the dal register. bits 0~3 of the dal register are always read as zero. note that the 12-bit dac data format should be unsigned. there are 8 levels of volume which are setup using the vol register. the highest 3 bits of this register are used for volume control. the misc register is used to control the dac, audio power amplifer and mute functions enable or not.

vol register bit 7 6 5 4 3 2 1 0 name vol? vol1 vol0 r/w r/w r/w r/w por 0 0 0 bit 7~5 vo2~vo0 : dac volume control data bit 4~0 unimplemented, read as 0 the programmer can change the dac volume by only writing the volume control data to the bits 7~5 of the vol, and bits 4~0 of the vol register are always read as zero. note that the 12-bit dac data format should be unsigned. vol [2:0] dac volume control 111 high vo ?ume 110 101 100 011 010 001 000 low vo ?ume
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 134 ???i? 01? ? 011 rev. 1.00 135 ???i? 01? ? 011 misc register bit 7 6 5 4 3 2 1 0 name lxtlp p ?em p ?en d?cen r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 p: low speed crystal oscillator power control, describe d elsewhere 0: disable 1: enable bit 6 pem: audio mute function control 0: mute disable 1: mute enable bit 5 pe: audio power amplifer function control 0: disable 1: enable bit 4~2 unimplemented bit 1 dce: dac control 0: disable 1: enable bit 0 unimplemented audio power amplifer power amplifer this device contains an audio power amplifer which is an integrated class ab monophonic type speaker driver. it has the properties of high s/n ratio, high slew rate, low distortion, large output oltage swing, excellent power supply ripple rejection, low power consumption, low standby current and power off control etc.
note: aud in: audio input v bias : speaker non-inverting input voltage reference sp+:audio positive output spC: audio negative output outp rising time (t r ) when the paen bit dacc register enables the power amplifer, note that it requires a certain time before it can output fully on the outp pin. however, this delay time depends on the value of c1. the c1 capacitor is connected between vbias and vss.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 136 ???i? 01? ? 011 rev. 1.00 137 ???i? 01? ? 011 capacitor voltage t r for battery based applications, power consumption is a key issue, therefore the amplifer should be turned off when in the standby state. in order to eliminate any speaker sound bursts while turning the amplifer on, the application circuit, which will incorporate a capacitance value of c1, should be adjusted in accordance with the speaker s audio frequency response. a greater value of c1 will improve the noise burst while turning on the amplifer. the recommended operation sequence is: turn on: audio signal standby (1/2vdd) enable amplifer wait t r for amplifer ready audio output turn off: audio signal fnished disable amplifer wait t r for amplifer off audio signal off if the application is not powered by batteries and there is no problem with amplifer on/off issues, a capacitor value of 0.1f for c1 is recommended. microphone amplifer th e device contains a m icrophone amplifer to enable easy interfacing to external microphones for recorder applications. amplifer overview the overall amplifier circuit contains several main features, pre-amp, agc (automatic gain control), power amplifer gain stage and a f our th -order low pass scf (switch ed capacitor filter). the following block diagram illustrates the main blocks of the microphone input control.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 136 ???i? 01? ? 011 rev. 1.00 137 ???i? 01? ? 011 amp pre - amp agc 4 order lpf adins 1 0 ain mout min agc filclk from timer 2 pd filout to adc rgs [ 2: 0 ] 2 ref _ gen ? vdd 0. 55 vdd micin 0.1 uf 0.1 uf 2.2 uf enbpa enbres the min pin is the amplifier m icrophone input pin to which external microcphones can be ac- couple d using a series capacitor. the microphone signal is amplifed and output on the mout pin. the voltage gain of the pre-amp is determined by the voltage level on the agc pin. an external capacitor ac couples the mout output to the ain pin. automatic gain control register C agcc the agcc register controls the overall function of the agc circuit such as enable /disable, gain control etc. agcc register bit 7 6 5 4 3 2 1 0 labe? ron ?gcen ?dins rgs? rgs1 rgs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 7 ro: agc charge resistance control 0: off 1: on bit 6 ce : agc control 0: disable 1: enable note that if the agc function is enabled, then pin pa0 will become an input pin and will disable any interal pull high options automatically.the agc function can be disabled to reduce power consumption. bit 5 dis : adc input control 0: not fltered via the scf 1: fltered via the scf bit 4-3 unimplemented , read as 0. bit 2-0 amplifer gain control 000: 1.16 001: 1.56 010: 2.22 011: 2.91 100: 5.09 101: 8.91 110: 13.82 111: 25.97
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 138 ???i? 01? ? 011 rev. 1.00 139 ???i? 01? ? 011 automatic gain control C agc the purpose of the automatic gain control (agc) is to dynamically adjust the p re- a mp gain, and therefore extend the dynamic range of input signals which can be applied the m icrophone input without distortion. the agc considerably extends the range of recordable sounds from whisper s to loud input voices. if the input signal to the agc increases sharply , the agc output response will be to create an increasing voltage on its output. th is increas ing output voltage will have the effect of reducing the p re- a mp gain thus compensating for the higher input signal. similarly, i f the input level decreases sharply, the agc output response will be to create a decreasing voltage on its output. this decreasing output voltage will have the effect of increasing the pre-amp gain thus compensating for the lower input signal. peak voltage levels at the amp output are detected by the agc circuit ry , which charge the external capacitor on the agc control pin. the internal source resistance of the agc circuit and external capacitor value determine the attack time of the gain control. the attack time is defned as the time needed for the agc to respond to a sudden increase of the input signal until the output signal is stable.the release time is determined by the rc time constant of the external (or internal using register bit ron) resistor and capacitor on the agc pin. the release time is defned as the time needed to respond to as a sudden decrease of the input signal until the output signal is stable. the internal two-stage amplifer is used to amplify the micropho ne input audio signal. this amplifed audio signal will be output both to the aout pin and to the internal adc input. the adins bit in the agcc register is used to control the adc input signal path, to determine if it is to be fltered by the scf flter or not. in this way, the audio signal can be converted into digital data for recording into the external flash memory using the spi interface. the gain of pre-amp amplifer is controlled by the voltage level of agc pin. the following fgure illustrates the relationship between pre-amp gain and the voltage level on the vagc pin. pre- amp gain -15.00 -10.00 -5.00 0.00 5.00 10.00 15.00 20.00 25.00 0.5 1 1.5 2 2.5 3 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 vagc (v) gain (db)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 138 ???i? 01? ? 011 rev. 1.00 139 ???i? 01? ? 011 two-stage amplifer the amplifcation of the agc loop is implemented using a two -stage a mplifers, one of which is a p re- a mp and amp. the agc dynamically monitors the output of the second stage amplifer s ignal level and set s the gain control voltage of the pre-amp accordingly . the pre-amp gain will be automatically adjusted to maintain an optimum signal level to the next stage of this agc loop. the gain of the second amplifer stage is controlled by the rgs2~rgs0 bits in the agcc register. there are eight amplifer gain level s . once a specifc gain is selected, the agc will refer ence itself to this gain level and adjust the pre-amp amplifer gain accordingly . using this method applications can select the most suitable gain levels according to their product requiremets. switched capacitor filter C scf the scf is used to flter out unwanted high frequency signal. this flter is a fourth order low pass scf type whose characteristics are selected according to the ficlk frequency. the filclk frequency is generated by the timer/event counter. the following table shows the 3-db breakpoint of the scf flter with respect to the filclk . input sample rate (khz) 3-db frequency (khz) filclk (khz) 6.0 ?.6 75 8.0 3.4 96 10.0 4.3 1?0 1?.0 5.? 146 16.0 6.9 195 the scf output can be sampled by the fast 12-bit a/d converter. in order to prevent unwanted noise, the adc will start to convert the input signal after skipping a few data samples. the relationship between filclk, adclk and the start conver sion signal is shown in the following diagram. filter _ clk t ?u?se _ high ( ty?ica? 96 khz ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 st?rt tck? tckh tadck tst tsta?t sam??e ?hase ( inte?na? timing ) p?e - sam??e ?hase ( inte?na? timing ) conve?sion ?hase ( inte?na? timing ) eocb tdeoc d [ 11 : 0 ] tdout ?don ton 000 h toff ?dclk tst 3 filter _ vout valid ( hold ) invalid ( sample ) valid (hold ) ( ?na?og ) t ?dc _ smp t st tsta?t t ?dc _ smp ? t ?u?se _ ?ow scf clock the scf clock source is generated by the timer/event counter . the timer/event counter operation mode should be selected to be the time r mode, therefore the tmr1 and tmr0 bits should be set to 1 0 . the timer/event counter can be used to generate a variable frequency clock according to the desired filclk cloc k source for the scf filter. a 3-bit prescaler , setup using bits tps0 ~ tps2 define the different division ratio s of the timer/event counter clock source. r e fer to the timer/ event counter section of the datasheet for more setup details. note that the timer/event counter output has its own interrupt source. if the timer/event counter is selected as the scf clock source, then the interrupt should be disabled to maintain an accurate scf clock source.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 140 ???i? 01? ? 011 rev. 1.00 141 ???i? 01? ? 011

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? ? ?? ? ? tmr structure confguration options confguration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high s?eed system osci??ato? se?ection - f h: 1. hxt ?. erc 3. hirc ? low s?eed system osci??ato? se?ection - f l: 1. lxt ?. lirc 3 f sub c?ock sou?ce 1. lxt ?. lirc 4 wdt c ?ock se?ection - f s: 1. f sub ?. f sys /4 5 hirc f?equency se?ection: 1. 4mhz ?. 8mhz 3. 1?mhz 6 f tbc c?ock sou?ce 1. lxt ?. lirc reset pin options 7 pb0/res pin o?tions: 1. res ?in ?. i/o ?in watchdog options 8 watchdog time ? function: 1. enab?e ?. disab?e 9 clrwdt inst ?uctions se?ection: 1. 1 inst?uctions ?. ? inst?uctions lvr options 10 lvr function: 1. enab?e ?. disab?e
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 140 ???i? 01? ? 011 rev. 1.00 141 ???i? 01? ? 011 no. options 11 lvr vo ?tage se?ection: 1. ?.10v ?. ?.55v 3. 3.15v 4. 4.?0v sim options 1? spi0 - wcol bit: 1. enab?e ?. disab?e 13 spi0 - csen bit: 1. enab?e ?. disab?e 14 i ? c0 - rnic bit: 1. enab?e ?. disab?e 15 i ? c0 debounce time se ?ection: 1. no debounce ?. 1 system c?ock debounce 3. ? system c?ock debounce 16 sim1 function: 1. enab?e ?. disab?e 17 spi1 - wcol bit: 1. enab?e ?. disab?e 18 spi1 - csen bit: 1. enab?e ?. disab?e 19 i ? c1 - rnic bit: 1. enab?e ?. disab?e ?0 i ? c1 debounce time se ?ection: 1. no debounce ?. 1 system c?ock debounce 3. ? system c?ock debounce
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 14? ???i? 01? ? 011 rev. 1.00 143 ???i? 01? ? 011 application circuits v33 vdd ? vdd1 vdd1 v33 vdd vdd ? vdd v33 v33 vdd v33 vdd vdd vdd v33 vdd vdd v33 vdd1 vdd1 v33 vdd vss? vss1 sk so pb6 pc5 pc0 p?7 si p?1 pc ? pb7 pc1 pc3 cs p?? p?? pc5 pc3 so resb p?3 p?0 p?5 p?0 vdd resb pc1 pc4 so sk vss cs si si pc ? pb6 p?3 so p?? pc0 vdd si vss p?7 p?4 pb7 p?1 cs p?4 vss vss sk sk p?5 vss pc4 p?6 p?6 c55 10u d1 powe ? led c50 100u r11 10 c49 10u bt1 b? ttery 1 ? j ?1 mini usb con 1 ? 3 4 5 vdd usb- usb+ vss vss sw ? 4 power switch ? 1 3 d? 1n5817 r13 0 c56 0.1u r14 0 r1 ? 0 c57 0.1u r9 330 u3 ht7 ? 33 ? 3 1 vin vout gnd s3 1 ? r ? 3 330 d4 pl ?y led s6 1 ? r18 47k + c m1 10u r ? 4 330 s5 1 ? ls1 spe?ker c60 0.01u c16 0.1u c63 0.1u d5 vo ? _1 d6 vo ? _ ? r ? 5 330 r ? 9 ? m c44 100u s1 1 ? c5 ? 10u u14 mx ? 5l1 ? 845e(16-sop 300mi ? ) 1 ? 3 4 5 6 7 8 16 15 14 13 1 ? 11 10 9 nc vcc nc nc nc nc cs# so sclk si nc nc nc nc gnd wp# d10 vo ? _6 c ? 1 0.1u c61 0.1u vr1 50k r6 100k c65 0.1u sw3 jumper 3 ? d3 rec led r m ? 6.8k r m1 4.7k r19 47k mk1 mic ? o ? hone ? 1 r ? 1 330 d7 vo ? _3 u1 ht83f ?? 48-lqfp 1 ? 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 4 ? 41 40 39 38 36 35 34 33 3 ? 31 30 ? 9 ? 8 ? 7 ? 6 ? 3 ?? ? 1 ? 0 19 18 17 16 15 14 13 1 ? ? 4 37 ? 5 sck ? sdo ? pc ? pc3 pc4 pc5 pc0 pc1 pc6 pc7 pb0 scsb ? sdi ? vcc ?5 vdd vcc ?? vss vss?? pb5 p?7 p?6 spn vcc ?7 spp ? ud_in ? ud vss?8 vcc ?8 vcc ?6 vss?6 vbi ?s ?gc mi n p?0/ ? out p?1 p?? p?3 p?4 p?5 pb7 pb6 pb4/xt ? pb3/xt1 pb? /osc ? pb1/osc1 ? in vss?7 mou t c6 ? 0.1u d9 vo ? _5 c64 0.1u s4 1 ? sw9 reset 1 ? r ?? 330 d8 vo ? _4 r ? 6 330 c ? 8 0.1u c59 0.1u jp14 e-w ? ite? ?? us con 1 3 5 7 9 11 13 15 17 19 ? 4 6 8 10 1 ? 14 16 18 ? 0 1 3 5 7 9 11 13 15 17 19 ? 4 6 8 10 1 ? 14 16 18 ? 0 r7 330 c ?? 0.1u s? 1 ? u15 mx ? 5l1606e(8-sop ? 00mi ? ) 1 ? 3 4 8 7 6 5 cs# so wp# gnd vcc hold# sclk si s7 1 ? c51 0.1u c58 ? . ? u on off adc/dac/agc power power amp power power circuit key6 key5 led & key connector key2 key3 spi flash key4 key7 key1
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 14? ???i? 01? ? 011 rev. 1.00 143 ???i? 01? ? 011 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 144 ???i? 01? ? 011 rev. 1.00 145 ???i? 01? ? 011 rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "halt" instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 144 ???i? 01? ? 011 rev. 1.00 145 ???i? 01? ? 011 instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic ?dd ??[m] ?dd data memo?y to ?cc 1 z? c? ?c? ov ?ddm ??[m] ?dd ?cc to data memo?y 1 note z? c? ?c? ov ?dd ??x ?dd immediate data to ?cc 1 z? c? ?c? ov ?dc ??[m] ?dd data memo?y to ?cc with ca??y 1 z? c? ?c? ov ?dcm ??[m] ?dd ?cc to data memo?y with ca??y 1 note z? c? ?c? ov sub ??x subt?act immediate data f?om the ?cc 1 z? c? ?c? ov sub ??[m] subt?act data memo?y f?om ?cc 1 z? c? ?c? ov subm ??[m] subt?act data memo?y f?om ?cc with ?esu?t in data memo?y 1 note z? c? ?c? ov sbc ??[m] subt?act data memo?y f?om ?cc with ca??y 1 z? c? ?c? ov sbcm ??[m] subt?act data memo?y f?om ?cc with ca??y ? ?esu?t in data memo?y 1 note z? c? ?c? ov d?? [m] decima? adjust ?cc fo? ?ddition with ?esu?t in data memo?y 1 note c logic operation ?nd ??[m] logica? ?nd data memo?y to ?cc 1 z or ??[m] logica? or data memo?y to ?cc 1 z xor ??[m] logica? xor data memo?y to ?cc 1 z ?ndm ??[m] logica? ?nd ?cc to data memo?y 1 note z orm ??[m] logica? or ?cc to data memo?y 1 note z xorm ??[m] logica? xor ?cc to data memo?y 1 note z ?nd ??x logica? ?nd immediate data to ?cc 1 z or ??x logica? or immediate data to ?cc 1 z xor ??x logica? xor immediate data to ?cc 1 z cpl [m] com??ement data memo?y 1 note z cpl? [m] com??ement data memo?y with ?esu?t in ?cc 1 z increment & decrement inc? [m] inc?ement data memo?y with ?esu?t in ?cc 1 z inc [m] inc?ement data memo?y 1 note z dec? [m] dec?ement data memo?y with ?esu?t in ?cc 1 z dec [m] dec?ement data memo?y 1 note z rotate rr? [m] rotate data memo?y ?ight with ?esu?t in ?cc 1 none rr [m] rotate data memo?y ?ight 1 note none rrc? [m] rotate data memo?y ?ight th?ough ca??y with ?esu?t in ?cc 1 c rrc [m] rotate data memo?y ?ight th?ough ca??y 1 note c rl? [m] rotate data memo?y ?eft with ?esu?t in ?cc 1 none rl [m] rotate data memo?y ?eft 1 note none rlc? [m] rotate data memo?y ?eft th?ough ca??y with ?esu?t in ?cc 1 c rlc [m] rotate data memo?y ?eft th?ough ca??y 1 note c
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 146 ???i? 01? ? 011 rev. 1.00 147 ???i? 01? ? 011 mnemonic description cycles flag affected data move mov ??[m] move data memo?y to ?cc 1 none mov [m]?? move ?cc to data memo?y 1 note none mov ??x move immediate data to ?cc 1 none bit operation clr [m].i c?ea? bit of data memo?y 1 note none set [m].i set bit of data memo?y 1 note none branch jmp add ? jum? unconditiona??y ? none sz [m] ski? if data memo?y is ze?o 1 note none sz? [m] ski? if data memo?y is ze?o with data movement to ?cc 1 note none sz [m].i ski? if bit i of data memo?y is ze?o 1 note none snz [m].i ski? if bit i of data memo?y is not ze?o 1 note none siz [m] ski? if inc?ement data memo?y is ze?o 1 note none sdz [m] ski? if dec?ement data memo?y is ze?o 1 note none siz? [m] ski? if inc?ement data memo?y is ze?o with ?esu?t in ?cc 1 note none sdz? [m] ski? if dec?ement data memo?y is ze?o with ?esu?t in ?cc 1 note none c? ll add? sub?outine ca?? ? none ret retu?n f?om sub?outine ? none ret ??x retu?n f?om sub?outine and ?oad immediate data to ?cc ? none reti retu?n f?om inte??u?t ? none table read t ?brdc [m] read tab?e (cu??ent ? age) to tblh and data memo?y ? note none t ? brdl [m] read tab?e (?ast ? age) to tblh and data memo?y ? note none miscellaneous nop no o?e?ation 1 none clr [m] c?ea? data memo?y 1 note none set [m] set data memo?y 1 note none clr wdt c?ea? watchdog time? 1 to ? pdf clr wdt1 p?e-c?ea? watchdog time? 1 to ? pdf clr wdt? p?e-c?ea? watchdog time? 1 to ? pdf sw ? p [m] swa? nibb?es of data memo?y 1 note none sw ?p ? [m] swa? nibb?es of data memo?y with ?esu?t in ?cc 1 none h? lt ente? ?owe? down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 146 ???i? 01? ? 011 rev. 1.00 147 ???i? 01? ? 011 instruction defnition ?dd data memo?y to ?cc with ca??y the contents of the specifed data memory, accumulator and the carry fag are added. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc + [m] + c ov ? z? ?c? c ?dd ?cc to data memo?y with ca??y the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. [m] ?cc + [m] + c ov ? z? ?c? c ?dd data memo?y to ?cc the contents of the specifed data memory and the accumulator are added. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc + [m] ov ? z? ?c? c ?dd immediate data to ?cc the contents of the accumulator and the specifed immediate data are added. the ?esu?t is sto?ed in the ?ccumu?ato? . ?c ?cc + x ov ? z? ?c? c ?dd ?cc to data memo?y the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. [m] ?cc + [m] ov ? z? ?c? c logica? ?nd data memo?y to ?cc data in the accumulator and the specifed data memory perform a bitwise logical ?nd o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " ?nd " [m] z logica? ?nd immediate data to ?cc data in the ?ccumu?ato? and the s?ecified immediate data ?e?fo? m a bitwise ?ogica? ?nd o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " ?nd " x z logica? ?nd ?cc to data memo?y data in the specifed data memory and the accumulator perform a bitwise logical ?nd o?e? ation. the ?esu?t is sto?ed in the data memo? y. [m] ?cc " ?nd " [m] z adc a,[m] desc?i?tion o?e?ation affected fag(s) adcm a,[m] desc?i?tion o?e?ation affected fag(s) add a,[m] desc?i?tion o?e?ation affected fag(s) add a,x desc?i?tion o?e?ation affected fag(s) addm a,[m] desc?i?tion o?e?ation affected fag(s) and a,[m] desc?i?tion o?e?ation affected fag(s) and a,x desc?i?tion o?e?ation affected fag(s) andm a,[m] desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 148 ???i? 01? ? 011 rev. 1.00 149 ???i? 01? ? 011 sub?outine ca?? unconditionally calls a subroutine at the specifed address. the program counter then inc ? ements by 1 to obtain the add? ess of the next inst ? uction which is then ? ushed onto the stack. the s?ecified add?ess is then ?oaded and the ??og? am continues execution f ? om this new add ? ess. ? s this inst? uction ? equi ? es an additiona? o?e?ation? it is a two cyc?e inst?uction. stack p?og?am counte? + 1 p?og?am counte? add? none c?ea? data memo?y each bit of the specifed data memory is cleared to 0. [m] 00h none c?ea? bit of data memo?y bit i of the specifed data memory is cleared to 0. [m].i 0 none c?ea? watchdog time? the to, pdf fags and the wdt are all cleared. wdt c ?ea?ed to 0 pdf 0 to ? pdf p?e-c?ea? watchdog time? the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt ? and must be executed a?te?nate? y with clr wdt? to have effect. re ?etitive? y executing this inst? uction without a?te?nate? y executing clr wdt? wi?? have no effect. wdt c ?ea?ed to 0 pdf 0 to ? pdf p?e-c?ea? watchdog time? the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed a ?te?nate? y with clr wdt1 to have effect. re ?etitive? y executing this inst? uction without a?te?nate? y executing wdt c ?ea?ed to 0 pdf 0 to ? pdf call addr desc?i?tion o?e?ation affected fag(s) clr [m] desc?i?tion o?e?ation affected fag(s) clr [m].i desc?i?tion o?e?ation affected fag(s) clr wdt desc?i?tion o?e?ation affected fag(s) clr wdt1 desc?i?tion o?e?ation affected fag(s) clr wdt2 desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 148 ???i? 01? ? 011 rev. 1.00 149 ???i? 01? ? 011 com??ement data memo?y each bit of the s ?ecified data memo? y is ?ogica??y com?? emented (1 ' s com ?? ement). bits which ?? evious ? y contained a 1 a? e changed to 0 and vice ve?sa. [m] [m] z com??ement data memo?y with ?esu?t in ?cc each bit of the s ?ecified data memo? y is ?ogica??y com?? emented (1 ' s com ?? ement). bits which ?? evious ? y contained a 1 a? e changed to 0 and vice ve? sa. the com??emented ?esu?t is sto?ed in the ?ccumu?ato? and the contents of the data memo?y ?emain unchanged. ?cc [m] z decima?-?djust ?cc fo? addition with ?esu?t in data memo?y conve?t the contents of the ?ccumu?ato? va?ue to a bcd ( bina? y coded decima?) va?ue ?esu? ting f?om the ?? evious addition of two bcd va?iab? es. if the ?ow nibb?e is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibb? e. othe? wise the ? ow nibb?e ? emains unchanged. if the high nibb? e is g?eate? than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentia??y ? the decima? conve?sion is ?e?fo?med by adding 00h? 06h? 60h o? 66h depending on the accumulator and fag conditions. only the c fag may be affected by this inst ? uction which indicates that if the o?igina? bcd sum is g?eate? than 100? it a??ows mu?ti??e ??ecision decima? addition. [m] ?cc + 00h o? [m] ?cc + 06h o? [m] ?cc + 60h o? [m] ?cc + 66h c dec?ement data memo?y data in the specifed data memory is decremented by 1. [m] [m] C 1 z dec?ement data memo?y with ?esu?t in ?cc data in the specifed data memory is decremented by 1. the result is stored in the ?ccumu?ato? . the contents of the data memo ?y ?emain unchanged. ?cc [m] C 1 z cpl [m] desc?i?tion o?e?ation affected fag(s) cpla [m] desc?i?tion o?e?ation affected fag(s) daa [m] desc?i?tion o?e?ation affected fag(s) dec [m] desc?i?tion o?e?ation affected fag(s) deca [m] desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 150 ???i? 01? ? 011 rev. 1.00 151 ???i? 01? ? 011 ente? ?owe? down mode this inst?uction sto?s the ??og?am execution and tu? ns off the system c? ock. the contents of the data memo ?y and ?egiste?s a?e ? etained. the wdt and ??esca?e? a? e c?ea? ed. the ?owe? down f? ag pdf is set and the wdt time-out f? ag to is c?ea?ed. to 0 pdf 0 to ? pdf inc?ement data memo?y data in the specifed data memory is incremented by 1. [m] [m]+1 z inc?ement data memo?y with ?esu?t in ?cc data in the specifed data memory is incremented by 1. the result is stored in the ?ccumu?ato? . the contents of the data memo ?y ?emain unchanged. ?cc [m]+1 z jum? unconditiona??y the contents of the p ?og? am counte? a?e ?e?? aced with the s? ecified add? ess. p? og ? am execution then continues f? om this new add ? ess. ? s this ? equi ? es the inse? tion of a dummy inst?uction whi?e the new add?ess is ?oaded? it is a two cyc?e inst?uction. p?og?am counte? add? none move data memo?y to ?cc the contents of the specifed data memory are copied to the accumulator. ?cc [m] none move immediate data to ?cc the immediate data specifed is loaded into the accumulator. ?cc x none move ?cc to data memo?y the contents of the accumulator are copied to the specifed data memory. [m] ?cc none no o?e?ation no o?e?ation is ?e?fo?med. execution continues with the next inst?uction. no o?e?ation none halt desc?i?tion o?e?ation affected fag(s) inc [m] desc?i?tion o?e?ation affected fag(s) inca [m] desc?i?tion o?e?ation affected fag(s) jmp addr desc?i?tion o?e?ation affected fag(s) mov a,[m] desc?i?tion o?e?ation affected fag(s) mov a,x desc?i?tion o?e?ation affected fag(s) mov [m],a desc?i?tion o?e?ation affected fag(s) nop desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 150 ???i? 01? ? 011 rev. 1.00 151 ???i? 01? ? 011 logica? or data memo?y to ?cc data in the accumulator and the specifed data memory perform a bitwise logical or o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " or " [m] z logica? or immediate data to ?cc data in the ?ccumu?ato? and the s?ecified immediate data ?e?fo? m a bitwise ?ogica? or o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " or " x z logica? or ?cc to data memo?y data in the specifed data memory and the accumulator perform a bitwise logical or o?e? ation. the ?esu?t is sto?ed in the data memo? y. [m] ?cc " or " [m] z retu?n f?om sub?outine the p?og?am counte? is ?esto?ed f? om the stack. p?og?am execution continues at the ?esto?ed add?ess. p?og?am counte? stack none retu?n f?om sub?outine and ?oad immediate data to ?cc the p?og?am counte? is ?esto?ed f?om the stack and the ?ccumu?ato? ? oaded with the specifed immediate data. program execution continues at the restored add?ess. p?og?am counte? stack ?cc x none retu?n f?om inte??u?t the p?og?am counte? is ?esto?ed f? om the stack and the inte??u?ts a?e ?e-enab?ed by setting the emi bit. emi is the maste ? inte??u?t g?oba? enab? e bit. if an inte??u?t was ? ending when the reti inst? uction is executed? the ? ending inte??u?t ?outine wi?? be ??ocessed befo?e ?etu?ning to the main ??og?am. p?og?am counte? stack emi 1 none rotate data memo?y ?eft the contents of the s ? ecified data memo ?y a ? e ? otated ? eft by 1 bit with bit 7 ?otated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 none or a,[m] desc?i?tion o?e?ation affected fag(s) or a,x desc?i?tion o?e?ation affected fag(s) orm a,[m] desc?i?tion o?e?ation affected fag(s) ret desc?i?tion o?e?ation affected fag(s) ret a,x desc?i?tion o?e?ation affected fag(s) reti desc?i?tion o?e?ation affected fag(s) rl [m] desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 15? ???i? 01? ? 011 rev. 1.00 153 ???i? 01? ? 011 . rotate data memo?y ?eft with ?esu?t in ?cc the contents of the s?ecified data memo?y a?e ?otated ? eft by 1 bit with bit 7 ? otated into bit 0. the ?otated ?esu?t is sto?ed in the ?ccumu?ato? and the contents of the data memo?y ?emain unchanged. ?cc.(i+1) [m].i; (i = 0~6) ?cc.0 [m].7 none rotate data memo?y ?eft th?ough ca??y the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 c rotate data memo?y ?eft th?ough ca??y with ?esu?t in ?cc data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the ?otated ?esu?t is sto? ed in the ?ccumu?ato? and the contents of the data memo?y ?emain unchanged. ?cc.(i+1) [m].i; (i = 0~6) ?cc.0 c c [m].7 c rotate data memo?y ?ight the contents of the specifed data memory are rotated right by 1 bit with bit 0 ?otated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 none rotate data memo?y ?ight with ?esu?t in ?cc data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 ? otated into bit 7. the ?otated ?esu?t is sto?ed in the ?ccumu?ato ? and the contents of the data memo?y ?emain unchanged. ?cc.i [m].(i+1); (i = 0~6) ?cc.7 [m].0 none rotate data memo?y ?ight th?ough ca??y the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 c rla [m] desc?i?tion o?e?ation affected fag(s) rlc [m] desc?i?tion o?e?ation affected fag(s) rlca [m] desc?i?tion o?e?ation affected fag(s) rr [m] desc?i?tion o?e?ation affected fag(s) rra [m] desc?i?tion o?e?ation affected fag(s) rrc [m] desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 15? ???i? 01? ? 011 rev. 1.00 153 ???i? 01? ? 011 rotate data memo?y ?ight th?ough ca??y with ?esu?t in ?cc data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated ?esu?t is sto?ed in the ?ccumu?ato? and the contents of the data memo?y ? emain unchanged. ?cc.i [m].(i+1); (i = 0~6) ?cc.7 c c [m].0 c subt?act data memo?y f?om ?cc with ca??y the contents of the specifed data memory and the complement of the carry fag a?e subt?acted f? om the ?ccumu?ato? . the ?esu?t is sto?ed in the ?ccumu?ato? . note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc C [m] C c ov ? z? ?c? c subt?act data memo?y f?om ?cc with ca??y and ?esu?t in data memo?y the contents of the specifed data memory and the complement of the carry fag a?e subt? acted f? om the ?ccumu?ato? . the ?esu? t is sto? ed in the data memo? y. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc C [m] C c ov ? z? ?c? c ski? if dec?ement data memo?y is 0 the contents of the specifed data memory are frst decremented by 1. if the result is 0 the fo?? owing inst? uction is ski??ed. ?s this ?equi? es the inse? tion of a dummy inst?uction whi?e the next inst?uction is fetched? it is a two cyc?e inst? uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. [m] [m] C 1 ski? if [m] = 0 none ski? if dec?ement data memo?y is ze?o with ?esu?t in ?cc the contents of the specifed data memory are frst decremented by 1. if the result is 0? the fo?? owing inst? uction is ski?? ed. the ?esu? t is sto? ed in the ?ccumu?ato? but the specifed data memory contents remain unchanged. as this requires the inse? tion of a dummy inst?uction whi? e the next inst? uction is fetched? it is a two cyc? e inst? uction. if the ? esu? t is not 0 ? the ??og? am ?? oceeds with the fo ?? owing inst?uction. ?cc [m] C 1 ski? if ?cc = 0 none rrca [m] desc?i?tion o?e?ation affected fag(s) sbc a,[m] desc?i?tion o?e?ation affected fag(s) sbcm a,[m] desc?i?tion o?e?ation affected fag(s) sdz [m] desc?i?tion o?e?ation affected fag(s) sdza [m] desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 154 ???i? 01? ? 011 rev. 1.00 155 ???i? 01? ? 011 set data memo?y each bit of the specifed data memory is set to 1. [m] ffh none set bit of data memo?y bit i of the specifed data memory is set to 1. [m].1 1 none ski? if inc?ement data memo?y is 0 the contents of the specifed data memory are frst incremented by 1. if the result is 0? the fo?? owing inst? uction is ski??ed. ?s this ?equi? es the inse? tion of a dummy inst?uction whi? e the next inst? uction is fetched? it is a two cyc?e inst? uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. [m] [m] + 1 ski? if [m] = 0 none ski? if inc?ement data memo?y is ze?o with ?esu?t in ?cc the contents of the specifed data memory are frst incremented by 1. if the result is 0? the fo??owing inst?uction is ski?? ed. the ?esu?t is sto?ed in the ?ccumu?ato? but the specifed data memory contents remain unchanged. as this requires the inse? tion of a dummy inst? uction whi? e the next inst? uction is fetched? it is a two cyc?e inst? uction. if the ?esu? t is not 0 the ??og?am ?? oceeds with the fo?? owing inst?uction. ?cc [m] + 1 ski? if ?cc = 0 none ski? if bit i of data memo?y is not 0 if bit i of the specifed data memory is not 0, the following instruction is skipped. ?s this ?equi?es the inse?tion of a dummy inst?uction whi?e the next inst?uction is fetched? it is a two cyc? e inst? uction. if the ?esu? t is 0 the ??og?am ?? oceeds with the fo??owing inst?uction. skip if [m].i 0 none subt?act data memo?y f?om ?cc the specifed data memory is subtracted from the contents of the accumulator. the ? esu? t is sto ? ed in the ? ccumu ? ato ? . note that if the ? esu? t of subt ? action is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc C [m] ov ? z? ?c? c set [m] desc?i?tion o?e?ation affected fag(s) set [m].i desc?i?tion o?e?ation affected fag(s) siz [m] desc?i?tion o?e?ation affected fag(s) siza [m] desc?i?tion o?e?ation affected fag(s) snz [m].i desc?i?tion o?e?ation affected fag(s) sub a,[m] desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 154 ???i? 01? ? 011 rev. 1.00 155 ???i? 01? ? 011 subt?act data memo?y f?om ?cc with ?esu?t in data memo?y the specifed data memory is subtracted from the contents of the accumulator. the ?esu?t is sto? ed in the data memo? y. note that if the ?esu?t of subt? action is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. [m] ?cc C [m] ov ? z? ?c? c subt?act immediate data f?om ?cc the immediate data specifed by the code is subtracted from the contents of the ? ccumu ? ato? . the ? esu? t is sto? ed in the ? ccumu ? ato? . note that if the ? esu? t of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc C x ov ? z? ?c? c swa? nibb?es of data memo?y the ?ow-o?de? and high-o?de? nibb? es of the s? ecified data memo? y a? e inte?changed. [m].3~[m].0?[m].7 ~ [m].4 none swa? nibb?es of data memo?y with ?esu?t in ?cc the ?ow-o?de? and high-o?de? nibb? es of the s? ecified data memo? y a? e inte ? changed. the ?esu? t is sto?ed in the ?ccumu?ato? . the contents of the data memo?y ?emain unchanged. ? cc.3 ~ ?cc.0 [m].7 ~ [m].4 ? cc.7 ~ ?cc.4 [m].3 ~ [m].0 none ski? if data memo?y is 0 if the contents of the s ? ecified data memo?y is 0? the fo ??owing inst ? uction is ski??ed. ?s this ?equi?es the inse?tion of a dummy inst?uction whi? e the next inst?uction is fetched? it is a two cyc?e inst?uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. ski? if [m] = 0 none ski? if data memo?y is 0 with data movement to ?cc the contents of the specifed data memory are copied to the accumulator. if the va? ue is ze?o? the fo?? owing inst? uction is ski??ed. ?s this ?equi? es the inse? tion of a dummy inst?uction whi? e the next inst? uction is fetched? it is a two cyc?e inst?uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. ?cc [m] ski? if [m] = 0 none subm a,[m] desc?i?tion o?e?ation affected fag(s) sub a,x desc?i?tion o?e?ation affected fag(s) swap [m] desc?i?tion o?e?ation affected fag(s) swapa [m] desc?i?tion o?e?ation affected fag(s) sz [m] desc?i?tion o?e?ation affected fag(s) sza [m] desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 156 ???i? 01? ? 011 rev. 1.00 157 ???i? 01? ? 011 ski? if bit i of data memo?y is 0 if bit i of the specifed data memory is 0, the following instruction is skipped. as this ?equi? es the inse? tion of a dummy inst ? uction whi? e the next inst ? uction is fetched? it is a two cyc?e inst?uction. if the ?esu?t is not 0? the ??og?am ?? oceeds with the fo??owing inst?uction. ski? if [m].i = 0 none read tab?e (cu??ent ? age) to tblh and data memo?y the ?ow byte of the ??og?am code (cu??ent ?age) add?essed by the tab?e ?ointe? (tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] ??og?am code (?ow byte) tblh ??og?am code (high byte) none read tab?e (?ast ? age) to tblh and data memo?y the ? ow byte of the ?? og? am code ( ? ast ? age) add? essed by the tab ?e ? ointe? (tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] ??og?am code (?ow byte) tblh ??og?am code (high byte) none logica? xor data memo?y to ?cc data in the accumulator and the specifed data memory perform a bitwise logical xor o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " xor " [m] z logica? xor ?cc to data memo?y data in the specifed data memory and the accumulator perform a bitwise logical xor o?e? ation. the ?esu?t is sto?ed in the data memo? y. [m] ?cc " xor " [m] z logica? xor immediate data to ?cc data in the ?ccumu?ato? and the s?ecified immediate data ?e?fo? m a bitwise ?ogica? xor o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " xor " x z sz [m].i desc?i?tion o?e?ation affected fag(s) tabrdc [m] desc?i?tion o?e?ation affected fag(s) tabrdl [m] desc?i?tion o?e?ation affected fag(s) xor a,[m] desc?i?tion o?e?ation affected fag(s) xorm a,[m] desc?i?tion o?e?ation affected fag(s) xor a,x desc?i?tion o?e?ation affected fag(s)
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 156 ???i? 01? ? 011 rev. 1.00 157 ???i? 01? ? 011 package information 48-pin lqfp (7mmx7mm) outline dimensions 48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 package information 1 may 12, 2010 symbol dimensions in inch min. nom. max. ? 0.350 D 0.358 b 0.?7? D 0.?80 c 0.350 D 0.358 d 0.?7? D 0.?80 e D 0.0?0 D f D 0.008 D g 0.053 D 0.057 h D D 0.063 i D 0.004 D j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. ? 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.?0 D g 1.35 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.?0 0 D 7
HT83F22 a/d type recorder 8-bit flash mcu rev. 1.00 158 ???i? 01? ? 011 rev. 1.00 pb ???i? 01? ? 011 holtek semiconductor inc. (headquarters) no.3? c?eation rd. ii? science pa?k? hsinchu? taiwan te ?: 886-3-563-1999 fax: 886-3-563-1189 htt? ://www.ho?tek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-?? no. 3-?? yuanqu st.? nankang softwa?e pa?k? tai? ei 115? taiwan te ?: 886-?-?655-7070 fax: 886-?-?655-7373 fax: 886-?-?655-7383 (inte?nationa? sa?es hot?ine) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit ?? p?oductivity bui?ding? no.5 gaoxin m ?nd road? nanshan dist?ict? shenzhen? china 518057 te ?: 86-755-8616-9908? 86-755-8616-9308 fax: 86-755-8616-97?? holtek semiconductor (usa), inc. (north america sales offce) 467?9 f?emont b?vd.? f?emont? c? 94538? us? te ?: 1-510-?5?-9880 fax: 1-510-?5?-9885 htt? ://www.ho?tek.com co?y?ight ? ? 011 by holtek semiconductor inc. the info?mation a??ea? ing in this data sheet is be? ieved to be accu? ate at the time of ?ub? ication. howeve ?? ho? tek assumes no ?es?onsibi? ity a?ising f ? om the use of the s ? ecifications desc? ibed. the a??? ications mentioned he ? ein a? e used so?e? y fo? the ?u?? ose of i??ust? ation and ho? tek makes no wa?? anty o? representation that such applications will be suitable without further modifcation, nor recommends the use of its ?? oducts fo? a??? ication that may ??esent a ? isk to human ? ife due to ma?function o? othe?wise. ho?tek's ??oducts a?e not autho? ized fo? use as c?itica? com?onents in ?ife su??o?t devices o? systems. ho?tek ?ese?ves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at htt? ://www.ho?tek.com.tw

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